ATMEGA103-6AC Atmel, ATMEGA103-6AC Datasheet - Page 31

IC MCU 128K 6MHZ A/D 64TQFP

ATMEGA103-6AC

Manufacturer Part Number
ATMEGA103-6AC
Description
IC MCU 128K 6MHZ A/D 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AC

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA103-6AC
Manufacturer:
ATMEL
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1
External Interrupt Flag
Register – EIFR
External Interrupt Control
Register – EICR
0945I–AVR–02/07
• Bits 3..0 – INT3 - INT0: External Interrupt Request 3 - 0 Enable
When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The external interrupts are
always low-level triggered interrupts. Activity on any of these pins will trigger an interrupt
request even if the pin is enabled as an output. This provides a way of generating a soft-
ware interrupt. When enabled, a level-triggered interrupt will generate an interrupt
request as long as the pin is held low.
• Bits 7..4 – INTF7 - INTF4: External Interrupt 7 - 4 Flags
When an edge on the INT7 - INT4 pins triggers an interrupt request, the corresponding
Interrupt Flag, INTF7 - INTF4, becomes set (one). If the I-bit in SREG and the corre-
sponding interrupt enable bit, INT7 - INT4 in EIMSK, is set (one), the MCU will jump to
the Interrupt Vector. The flag is cleared when the corresponding interrupt routine is exe-
cuted. Alternatively, the flag is cleared by writing a logical “1” to it. These flags are
always cleared when INTF7 - INFT4 are configured as level interrupts.
• Bits 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
• Bits 7..0 – ISCX1, ISCX0: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7 - INT4 if the SREG
I-flag and the corresponding interrupt mask in the EIMSK are set. The level and edges
on the external pins that activate the interrupts are defined in Table 9.
Table 9. Interrupt Sense Control
The value on the INTX pin is sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock fre-
quency can be lower than the XTAL frequency if the XTAL divider is enabled. If low-level
interrupt is selected, the low level must be held until the completion of the currently exe-
Bit
$38 ($58)
Read/Write
Initial Value
Bit
$3A ($5A)
Read/Write
Initial Value
ISCX1
0
0
1
1
ISCX0
INTF7
ISC71
R/W
R/W
0
1
0
1
7
0
7
0
INTF6
ISC70
Description
The low level of INTX generates an interrupt request.
Reserved
The falling edge of INTX generates an interrupt request.
The rising edge of INTX generates an interrupt request.
R/W
R/W
6
0
6
0
INTF5
ISC61
R/W
R/W
5
0
5
0
INTF4
ISC60
R/W
R/W
4
0
4
0
ISC51
R/W
R
3
0
3
0
ISC50
R/W
R
2
0
2
0
ATmega103(L)
ISC41
R/W
R
1
0
1
0
ISC40
R/W
R
0
0
0
0
EIFR
EICR
31

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