ATMEGA103-6AC Atmel, ATMEGA103-6AC Datasheet - Page 66

• Manufacturer Part Number: ATMEGA103-6AC
• Description: IC MCU 128K 6MHZ A/D 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA103-6AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UART
Data Transmission
66
ATmega103(L)
The ATmega103(L) features a full duplex (separate Receive and Transmit Registers)
Universal Asynchronous Receiver and Transmitter (UART). The main features are:
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A block schematic of the UART Transmitter is shown in Figure 41.
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register, UDR. Data is transferred from UDR to the Transmit Shift Register when:
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If the 10(11)-bit Transmit Shift Register is empty, data is transferred from UDR to the
Shift Register. At this time the UDRE (UART Data Register Empty) bit in the UART Sta-
tus Register, USR, is set. When this bit is set (one), the UART is ready to receive the
next character. Writing to UDR clears UDRE. At the same time as the data is transferred
from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit)
and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART
Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit
Shift Register.
Baud Rate Generator that can Generate a large Number of Baud Rates (bps)
High Baud Rates at Low XTAL Frequencies
8 or 9 Bits Data
Noise Filtering
OverRun Detection
Framing Error Detection
False Start Bit Detection
Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
A new character has been written to UDR after the stop bit from the previous
character has been shifted out. The Shift Register is loaded immediately.
A new character has been written to UDR before the stop bit from the previous
character has been shifted out. The Shift Register is loaded when the stop bit of the
character currently being transmitted has been shifted out.
0945I–AVR–02/07