ATMEGA103-6AC Atmel, ATMEGA103-6AC Datasheet - Page 77

• Manufacturer Part Number: ATMEGA103-6AC
• Description: IC MCU 128K 6MHZ A/D 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA103-6AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Analog-to-Digital
Converter
Feature list:
0945I–AVR–02/07
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The ATmega103(L) features a 10-bit successive approximation ADC. The ADC is con-
nected to an 8-channel Analog Multiplexer, which allows each pin of Port F to be used
as an input for the ADC. The ADC contains a Sample and Hold Amplifier, which ensures
that the input voltage to the ADC is held at a constant level during conversion. A block
diagram of the ADC is shown in Figure 45.
The ADC has two separate analog supply voltage pins, AV
be connected to GND, and the voltage on AV
V
these pins.
An external reference voltage must be applied to the AREF pin. This voltage must be in
the range AGND - AV
Figure 45. Analog-to-Digital Converter Block Schematic
CC
10-bit Resolution
±2 LSB Absolute Accuracy
0.5 LSB Integral Non-linearity
70 - 280 µs Conversion Time
Up to 14 kSPS
8 Multiplexed Input Channels
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
Reference
. See the section “ADC Noise Canceling Techniques” on page 82 on how to connect
External
Voltage
Analog
Inputs
8-BIT DATA BUS
CHANNEL
MUX
8-
CC
.
+
10-BIT DAC
-
SAMPLE & HOLD
COMPARATOR
ADC MULTIPLEXER
SELECT (ADMUX)
CC
must not differ more than ± 0.3V from
ADC CTRL & STATUS
ADC CONVERSION
REGISTER (ADCSR)
COMPLETE IRQ
ATmega103(L)
CC
CONVERSION LOGIC
and AGND. AGND must
9
ADC DATA REGISTER
(ADCH/ADCL)
0
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