ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 45

• Manufacturer Part Number: ATMEGA103-6AI
• Description: IC MCU 128K 6MHZ A/D IT 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA103-6AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Asynchronous Operation of
Timer/Counter0
0945I–AVR–02/07
• Bit 3 – AS0: Asynchronous Timer/Counter0
When set (one), Timer/Counter0 is clocked from the TOSC1 pin. When cleared (zero),
Timer/Counter0 is clocked from the internal system clock, CK. When the value of this bit
is changed, the contents of TCNT0 might get corrupted.
• Bit 2 – TCN0UB: Timer/Counter0 Update Busy
When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes
set (one). When TCNT0 has been updated from the temporary storage register, this bit
is cleared (zero) by hardware. A logical “0” in this bit indicates that TCNT0 is ready to be
updated with a new value.
• Bit 1 – OCR0UB: Output Compare Register0 Update Busy
When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes
set (one). When OCR0 has been updated from the temporary storage register, this bit is
cleared (zero) by hardware. A logical “0” in this bit indicates that OCR0 is ready to be
updated with a new value.
• Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy
When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes
set (one). When TCCR0 has been updated from the temporary storage register, this bit
is cleared (zero) by hardware. A logical “0” in this bit indicates that TCCR0 is ready to be
updated with a new value.
If a write is performed to any of the three Timer/Counter0 Registers while its update
busy flag is set (one), the updated value might get corrupted and cause an unintentional
interrupt to occur.
When reading TCNT0, OCR0 and TCCR0, there is a difference in result. When reading
TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the
temporary storage register is read.
When Timer/Counter0 operates synchronously, all operations and timing are identical to
Timer/Counter2. During asynchronous operation, however, some considerations must
be taken.
•
•
WARNING: When switching between asynchronous and synchronous clocking of
Timer/Counter0, the Timer Registers TCNT0, OCR0 and TCCR0 might get
corrupted. The following is the safe procedure for switching clock source:
1. Disable the Timer0 interrupts OCIE0 and TOIE0.
2. Select clock source by setting ASO as appropriate.
3. Write new values to TCNT0, OCR0 and TCCR0.
4. If switching to asynchronous operation, wait for TCNT0UB, OCR0UB and
5. Clear the Timer/Counter0 Interrupt Flags.
6. Enable interrupts if needed.
The Oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock
signal applied to this pin goes through the same amplifier having a bandwidth of
256 kHz. The external clock signal should therefore be in the interval 0 Hz -
256 kHz. The frequency of the clock signal applied to the TOSC1 pin must be lower
than one fourth of the CPU main clock frequency. Observe that CPU clock
frequency can be lower than the XTAL frequency if the XTAL divider is enabled.
TCR0UB to be cleared.
ATmega103(L)
45