ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 113

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Serial Downloading
Serial Programming
Algorithm
0945I–AVR–02/07
Both the Flash and EEPROM memory arrays can be programmed using the serial inter-
face while RESET is pulled to GND, or when PEN is low during Power-on Reset. The
serial interface consists of pins SCK, RXD/PDI (input) and TXD/PDO (output). After
RESET is set low, the Programming Enable instruction needs to be executed first before
program/erase instructions can be executed.
For the EEPROM, an auto-erase cycle is provided within the self-timed Write instruction
and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-
tion turns the content of every memory location in both the Program and EEPROM
arrays into $FF.
The Program and EEPROM memory arrays have separate address spaces: $0000 to
$FFFF for Program memory and $0000 to $0FFF for EEPROM memory.
Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
Figure 77. Serial Programming
INSTR. IN
DATA OUT
CLOCK IN
Note:
Instruction in and data out is not using the SPI pins as on other AVR devices. SCK uses
the SPI pin as usual.
When writing serial data to the ATmega103(L), data is sampled by the ATmega
103/103L on the rising edge of SCK. When reading data from the ATmega103(L), data
is clocked on the falling edge of SCK. See Figure 78 for an explanation. To program and
verify the ATmega103(L) in the Serial Programming mode, the following sequence is
recommended (See 4-byte instruction formats in Table 44.):
1. Power-up sequence: Apply power between V
are set to “0”. The RESET signal must be kept low during the complete serial
programming session. If a crystal is not connected across pins XTAL1 and
XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer
cannot guarantee that SCK is held low during Power-up. In this case, RESET
must be given a positive pulse of at least two XTAL1 cycles duration after SCK
has been set to “0”.
ATmega103(L)
ATmega103(L)
VCC
PE0 (PD1/RXD)
PE1 (PD0/TXD)
PB1 (SCK)
XTAL1
RESET
GND
and GND while RESET and SCK
CC
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