IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 12/141

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Program and Data
Addressing Modes
ATmega103(L)
12
The 4096 first Data memory locations address both the Register File, the I/O memory
and the internal Data SRAM. The first 96 locations address the Register File and I/O
memory, and the next 4000 locations address the internal Data SRAM.
An optional external Data SRAM can be used with the ATmega103(L). This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area
starts at the address following the internal SRAM. If a 64K external SRAM is used, 4K of
the external memory is lost as the addresses are occupied by internal memory.
When the addresses accessing the SRAM memory space exceeds the internal Data
memory locations, the external Data SRAM is accessed using the same instructions as
for the internal Data memory access. When the internal Data memories are accessed,
the read and write strobe pins (RD and WR) are inactive during the whole access cycle.
External SRAM operation is enabled by setting the SRE bit in the MCUCR Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, PUSH and
POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts,
subroutine calls and returns take two clock cycles extra because the 2-byte Program
Counter is pushed and popped. When external SRAM interface is used with wait state,
two additional clock cycles are used per byte. This has the following effect: Data transfer
instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns
will need four clock cycles more than specified in the “Instruction Set Summary” on page
135.
The five different addressing modes for the Data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The Indirect with Displacement mode features 63 address locations reached from the
base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic Pre-decrement and Post-
increment, the address registers X, Y, and Z are decremented and incremented.
The entire Data address space including the 32 general purpose working registers and
the 64 I/O Registers are all accessible through all these addressing modes. See the
next section for a detailed description of the different addressing modes.
The ATmega103(L) AVR RISC microcontroller supports powerful and efficient address-
ing modes for access to the Program memory (Flash) and Data memory (SRAM,
Register File and I/O memory). This section describes the different addressing modes
supported by the AVR architecture. In the figures, OP means the operation code part of
the instruction word. To simplify, not all figures show the exact location of the address-
ing bits.
0945I–AVR–02/07