ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 30

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Interrupt Handling
External Interrupt Mask
Register – EIMSK
ATmega103(L)
30
an external or Watchdog reset occurs, the source of reset can be found by using the fol-
lowing truth table, Table 8.
Table 8. Reset Source Identification
Reset Source
Watchdog Reset
Power-on Reset
External Reset
Power-on Reset
The ATmega103(L) has two dedicated 8-bit Interrupt Mask Control Registers; EIMSK
(External Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register).
In addition, other enable and mask bits can be found in the peripheral control registers.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual Interrupt Vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the Interrupt Flag will be set and remembered until the interrupt is enabled or the
flag is cleared by software.
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared
(zero), the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine or restored when returning from an interrupt routine. This must be handled by
software.
Bit
7
6
5
$39 ($59)
INT7
INT6
INT5
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bits 7..4 – INT7 - INT4: External Interrupt Request 7 - 4 Enable
When an INT7 - INT4 bit is set (one) and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control
bits in the External Interrupt Control Register (EICR) define whether the external inter-
rupt is activated on rising or falling edge or is level-sensed. Activity on any of these pins
will trigger an interrupt request even if the pin is enabled as an output. This provides a
way of generating a software interrupt.
EXTRF
PORF
0
0
1
1
4
3
2
1
INT4
INT3
INT2
INT1
INT0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0945I–AVR–02/07
0
1
0
1
0
EIMSK
0

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