IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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External Interrupt Flag
Register – EIFR
External Interrupt Control
Register – EICR
0945I–AVR–02/07
• Bits 3..0 – INT3 - INT0: External Interrupt Request 3 - 0 Enable
When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The external interrupts are
always low-level triggered interrupts. Activity on any of these pins will trigger an interrupt
request even if the pin is enabled as an output. This provides a way of generating a soft-
ware interrupt. When enabled, a level-triggered interrupt will generate an interrupt
request as long as the pin is held low.
Bit
7
6
5
$38 ($58)
INTF7
INTF6
INTF5
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bits 7..4 – INTF7 - INTF4: External Interrupt 7 - 4 Flags
When an edge on the INT7 - INT4 pins triggers an interrupt request, the corresponding
Interrupt Flag, INTF7 - INTF4, becomes set (one). If the I-bit in SREG and the corre-
sponding interrupt enable bit, INT7 - INT4 in EIMSK, is set (one), the MCU will jump to
the Interrupt Vector. The flag is cleared when the corresponding interrupt routine is exe-
cuted. Alternatively, the flag is cleared by writing a logical “1” to it. These flags are
always cleared when INTF7 - INFT4 are configured as level interrupts.
• Bits 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
Bit
7
6
5
$3A ($5A)
ISC71
ISC70
ISC61
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bits 7..0 – ISCX1, ISCX0: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7 - INT4 if the SREG
I-flag and the corresponding interrupt mask in the EIMSK are set. The level and edges
on the external pins that activate the interrupts are defined in Table 9.
Table 9. Interrupt Sense Control
ISCX1
ISCX0
Description
0
0
The low level of INTX generates an interrupt request.
0
1
Reserved
1
0
The falling edge of INTX generates an interrupt request.
1
1
The rising edge of INTX generates an interrupt request.
The value on the INTX pin is sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock fre-
quency can be lower than the XTAL frequency if the XTAL divider is enabled. If low-level
interrupt is selected, the low level must be held until the completion of the currently exe-
ATmega103(L)
4
3
2
1
INTF4
R/W
R
R
R
0
0
0
0
4
3
2
1
ISC60
ISC51
ISC50
ISC41
R/W
R/W
R/W
R/W
0
0
0
0
0
EIFR
R
0
0
ISC40
EICR
R/W
0
31