IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Timer/Counter Interrupt Mask
Register – TIMSK
0945I–AVR–02/07
Bit
7
6
$37 ($57)
OCIE2
TOIE2
TICIE1
Read/Write
R/W
R/W
R/W
Initial Value
0
0
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $0012) is executed if a compare match in Timer/Counter2 occurs, i.e., when the
OCF2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector
$0014) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is
set in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event interrupt is enabled. The corresponding interrupt
(at vector $0016) is executed if a capture-triggering event occurs on pin 29, PD4(IC1),
i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register.
• Bit 4 – OCE1A: Timer/Counter1 Output Compare A Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare A Match interrupt is enabled. The corresponding interrupt (at
vector $0018) is executed if a Compare A Match in Timer/Counter1 occurs, i.e., when
the OCF1A bit is set in the Timer/Counter Interrupt Flag Register.
• Bit 3 – OCIE1B: Timer/Counter1 Output Compare B Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare B Match interrupt is enabled. The corresponding interrupt (at
vector $001A) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when
the OCF1B bit is set in the Timer/Counter Interrupt Flag Register.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$001C) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is
set in the Timer/Counter Interrupt Flag Register.
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $001E) is executed if a compare match in Timer/Counter0 occurs, i.e., when the
OCF0 bit is set in the Timer/Counter Interrupt Flag Register.
ATmega103(L)
5
4
3
2
OCIE1A
OCIE1B
TOIE1
OCIE0
R/W
R/W
R/W
0
0
0
0
1
0
TOIE0
TIMSK
R/W
R/W
0
0
33