IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 36/141

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Interrupt Response Time
Sleep Modes
Idle Mode
ATmega103(L)
36
(Tim er/Co un ter1 Ove rflow Inte rrup t En able) an d TO V1 a re set (o ne) , th e
Timer/Counter1 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 advances from $0000.
• Bit 1 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and
the data in OCR0 – Output Compare Register 0. OCF0 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG and OCIE0 (Timer/Counter2
Compare Interrupt Enable) and the OCF0 are set (one), the Timer/Counter0 Output
Compare interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
(Tim er/Co un ter0 Ove rflow Inte rrup t En able) an d TO V0 a re set (o ne) , th e
Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter0 advances from $00.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. Four clock cycles after the Interrupt Flag has been set, the Program Vector
address for the actual interrupt handling routine is executed. During this four-clock-cycle
period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer
is decremented by 2. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes
four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is
popped back from the Stack, and the Stack Pointer is incremented by 2. When the AVR
exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a
SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register
select which sleep mode (Idle, Power-down, or Power-save) will be activated by the
SLEEP instruction, see Table 3 on page 23.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, exe-
cutes the interrupt routine and resumes execution from the instruction following SLEEP.
The contents of the Register File, SRAM, and I/O memory are unaltered. If a reset
occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the
Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC,
Timer/Counters, Watchdog and the interrupt system to continue operating. This enables
the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog
Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This
will reduce power consumption in Idle mode. When the MCU wakes up from Idle mode,
the CPU starts program execution immediately.
0945I–AVR–02/07