IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Timer/Counter1 – TCNT1H
and TCNT1L
0945I–AVR–02/07
• Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0
The lock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1.
Table 17. Clock1 Prescale Select
CS12
CS11
CS10
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
The Stop condition provides a Timer Enable/Disable function. The CK down divided
modes are scaled directly from the CK CPU clock. If the external pin modes are used for
Timer/Counter1, transitions on PD6/(T1) will clock the counter even if the pin is config-
ured as an output. This feature can give the user software control of the counting.
Bit
15
14
13
$2D ($4D)
MSB
$2C ($4C)
7
6
5
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To
ensure that both the high and low bytes are read and written simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary regis-
ter (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and
ICR1. If the main program and interrupt routines perform access to registers using
TEMP, interrupts must be disabled during access from the main program (and from
interrupt routines if interrupts are allowed from within interrupt routines).
TCNT1 Timer/Counter1 Write:
When the CPU writes to the High Byte TCNT1H, the written data is placed in the
TEMP Register. Next, when the CPU writes the Low Byte TCNT1L, this byte of data
is combined with the byte data in the TEMP Register, and all 16 bits are written to
the TCNT1 Timer/Counter1 Register simultaneously. Consequently, the High Byte
TCNT1H must be accessed first for a full 16-bit register write operation. When using
Timer/Counter1 as an 8-bit Timer, it is sufficient to write the Low Byte only.
TCNT1 Timer/Counter1 Read:
When the CPU reads the Low Byte TCNT1L, the data of TCNT1L is sent to the CPU
and the data of the High Byte TCNT1H is placed in the TEMP Register. When the
CPU reads the data in the High Byte TCNT1H, the CPU receives the data in the
TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a
ATmega103(L)
Description
Stop, the Timer/Counter1 is stopped.
CK
CK/8
CK/64
CK/256
CK/1024
External Pin T1, falling edge
External Pin T1, rising edge
12
11
10
9
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
8
TCNT1H
LSB
TCNT1L
0
R/W
R/W
0
0
51