IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 55/141

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Watchdog Timer
Watchdog Timer Control
Register – WDTCR
0945I–AVR–02/07
The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling the
Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
Table 21. See characterization data for typical values at other V
(Watchdog Reset) instruction resets the Watchdog Timer. From the Watchdog Reset,
eight different clock cycle periods can be selected to determine the reset period. If the
reset period expires without another Watchdog Reset, the ATmega103(L) resets and
executes from the Reset Vector. For timing details on the Watchdog Reset, refer to
page 29.
To prevent unintentional disabling of the Watchdog, a special turn-off procedure must
be followed when the Watchdog is disabled. Refer to the description of the Watchdog
Timer Control Register for details.
Figure 36. Watchdog Timer
Oscillator
1 MHz at V
= 5V
CC
350 kHz at V
= 3V
CC
Bit
7
6
5
$21 ($41)
Read/Write
R
R
R
Initial Value
0
0
0
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared, Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared
(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the
WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-
dure must be followed:
ATmega103(L)
levels. The WDR
CC
4
3
2
1
WDTOE
WDE
WDP2
WDP1
WDP0
R/W
R/W
R/W
R/W
0
0
0
0
0
WDTCR
R/W
0
55