IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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SS Pin Functionality
0945I–AVR–02/07
Figure 38. SPI Master-Slave Interconnection
MSB
MASTER
8-BIT SHIFT REGISTER
SPI
CLOCK GENERATOR
The system is single-buffered in the transmit direction and double-buffered in the
receive direction. This means that characters to be transmitted cannot be written to the
SPI Data Register before the entire shift cycle is completed. When receiving data, how-
ever, a received byte must be read from the SPI Data Register before the next byte has
been completely shifted in. Otherwise, the first byte is lost.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is
overridden according to the following table:
Table 22. SPI Pin Overrides
PIN
Direction, Master SPI
MOSI
User Defined
MISO
Input
SCK
User Defined
SS
User Defined
Note:
See “Alternate Functions of Port B” on page 89 for a detailed description and how to
define the direction of the user-defined SPI pins.
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine
the direction of the SS pin. If SS is configured as an output, the pin is a general output
pin that does not affect the SPI system. If SS is configured as an input, it must be held
high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry
when the SPI is configured as Master with the SS pin defined as an input, the SPI sys-
tem interprets this as another Master selecting the SPI as a Slave and starts to send
data to it. To avoid bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a
result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in
SREG is set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmittal is used in Master mode and there exists a
possibility that SS is driven low, the interrupt should always check that the MSTR bit is
still set. Once the MSTR bit has been cleared by a Slave Select, it must be set by the
user to re-enable SPI Master mode.
When the SPI is configured as a Slave, the SS pin is always input. When SS is held low,
the SPI is activated and MISO becomes an output if configured so by the user. All other
pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once
ATmega103(L)
LSB
MSB
SLAVE
MISO
MISO
8-BIT SHIFT REGISTER
MOSI MOSI
SCK
SCK
SS
SS
V
CC
Direction, Slave SPI
Input
User Defined
Input
Input
LSB
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