IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 

Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 62/141

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Data Modes
SPI Control Register – SPCR
ATmega103(L)
62
the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI
will stop sending and receiving immediately and both data received and data sent must
be considered as lost.
There are four combinations of SCK phase and polarity with respect to serial data that
are determined by control bits CPHA and CPOL. The SPI data transfer formats are
shown in Figure 39 and Figure 40.
Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0
SCK CYCLE #
1
2
(FOR REFERENCE)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MSB
(FROM MASTER)
MISO
MSB
(FROM SLAVE)
SS (TO SLAVE)
SAMPLE
* Not defined but normally MSB of character just received.
Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0
SCK CYCLE #
1
(FOR REFERENCE)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MSB
(FROM MASTER)
MISO
MSB
*
(FROM SLAVE)
SS (TO SLAVE)
SAMPLE
* Not defined but normally LSB of previously transmitted character.
Bit
7
6
5
$0D ($2D)
SPIE
SPE
DORD
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the Global Interrupts are enabled.
• Bit 6 – SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled and SS, MOSI, MISO and SCK are
connected to pins PB0, PB1, PB2 and PB3.
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2
1
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3
2
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1
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1
MSTR
CPOL
CPHA
SPR1
R/W
R/W
R/W
R/W
0
0
0
0
8
LSB
LSB
*
8
LSB
LSB
0
SPR0
SPCR
R/W
0
0945I–AVR–02/07