ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 67

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
0945I–AVR–02/07
Figure 41. UART Transmitter
DATA BUS
BAUD x 16
BAUD RATE
XTAL
GENERATOR
STORE UDR
SHIFT ENABLE
CONTROL LOGIC
IDLE
UART CONTROL
REGISTER (UCR)
On the baud rate clock following the transfer operation to the Shift Register, the start bit
is shifted out on the TXD pin, followed by the data, LSB first. When the stop bit has been
shifted out, the Shift Register is loaded if any new data has been written to the UDR dur-
ing the transmission. During loading, UDRE is set. If there is no new data in the UDR
Register to send when the stop bit is shifted out, the UDRE Flag will remain set. In this
case, after the stop bit has been present on TXD for one bit length, the TX Complete
Flag (TXC) in USR is set.
The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is
cleared (zero), the PE1 pin can be used for general I/O. When TXEN is set, the UART
Transmitter will be connected to PE1, which is forced to be an output pin regardless of
the setting of the DDE1 bit in DDRE.
ATmega103(L)
/16
UART I/O DATA
REGISTER (UDR)
1
BAUD
10(11)-BIT TX
SHIFT REGISTER
UART STATUS
REGISTER (USR)
DATA BUS
TXC
UDRE
IRQ
IRQ
PIN CONTROL
LOGIC
TXD
67

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