IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 78/141

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Operation
Prescaling
ATmega103(L)
78
The ADC operates in Single Conversion mode, and each conversion will have to be ini-
tiated by the user.
The ADC is enabled by writing a logical “1” to the ADC Enable bit, ADEN in ADCSR.
The first conversion that is started after enabling the ADC will be preceded by a dummy
conversion to initialize the ADC. To the user, the only difference will be that this conver-
sion takes 13 more ADC clock pulses than a normal conversion (see Figure 48).
A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC.
This bit will stay high as long as the conversion is in progress and be set to zero by hard-
ware when the conversion is completed. If a different data channel is selected while a
conversion is in progress, the ADC will finish the current conversion before performing
the channel change.
As the ADC generates a 10-bit result, two Data Registers, ADCH and ADCL, must be
read to get the result when the conversion is complete. Special data protection logic is
used to ensure that the contents of the Data Registers belong to the same result when
they are read. This mechanism works as follows:
When reading data, ADCL must be read first. Once ADCL is read, ADC access to Data
Registers is blocked. This means that if ADCL has been read, and a conversion com-
pletes before ADCH is read, none of the registers are updated and the result from the
conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers
is re-enabled.
The ADC has its own interrupt, ADIF, which can be triggered when a conversion com-
pletes. When ADC access to the Data Registers is prohibited between reading of ADCL
and ADCH, the interrupt will trigger even if the result is lost.
Figure 46. ADC Prescaler
ADEN
CK
ADPS0
ADPS1
ADPS2
The ADC contains a prescaler, which divides the system clock to an acceptable ADC
clock frequency. The ADC accepts input clock frequencies in the range 50 - 200 kHz.
Applying a higher input frequency will result in poorer accuracy (see “ADC DC Charac-
teristics” on page 83).
The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input fre-
quency from any XTAL frequency above 100 kHz. The prescaler starts counting from
the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler
Reset
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
0945I–AVR–02/07