IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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ADC Noise Canceler
Function
ADC Multiplexer Select
Register – ADMUX
ADC Control and Status
Register – ADCSR
ATmega103(L)
80
The ADC features a noise canceler that enables conversion during Idle mode to reduce
noise induced from the CPU core. To make use of this feature, the following procedure
should be used:
1. Turn off the ADC by clearing ADEN.
2. Turn on the ADC and simultaneously start a conversion by setting ADEN and
ADSC. This starts a dummy conversion that will be followed by a valid
conversion.
3. Within 14 ADC clock cycles, enter Idle mode.
4. If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the MCU and execute the ADC conversion complete interrupt
routine.
Bit
7
6
5
$07 ($27)
Read/Write
R
R
R
Initial Value
0
0
0
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
• Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2 - 0
The value of these three bits selects which analog input 7 - 0 is connected to the ADC.
Bit
7
6
5
$06 ($26)
ADEN
ADSC
Read/Write
R/W
R/W
R
Initial Value
0
0
0
• Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is
turned off. Turning the ADC off while a conversion is in progress will terminate this
conversion.
• Bit 6 – ADSC: ADC Start Conversion
A logical “1” must be written to this bit to start each conversion. The first time ADSC has
been written after the ADC has been enabled, or if ADSC is written at the same time as
the ADC is enabled, a dummy conversion will precede the initiated conversion. This
dummy conversion performs initialization of the ADC.
ADSC remains high during the conversion. ADSC goes low after the conversion is com-
plete, but before the result is written to the ADC Data Registers. This allows a new
conversion to be initiated before the current conversion is complete. The new conver-
sion will then start immediately after the current conversion completes. When a dummy
conversion precedes a real conversion, ADSC will stay high until the real conversion
completes.
Writing a zero to this bit has no effect.
4
3
2
1
0
MUX2
MUX1
MUX0
R
R
R/W
R/W
R/W
0
0
0
0
0
4
3
2
1
ADIF
ADIE
ADPS2
ADPS1
ADPS0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
ADMUX
0
ADCSR
0
0945I–AVR–02/07