IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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ADC Data Register – ADCL
and ADCH
0945I–AVR–02/07
• Bit 5 – Res: Reserved Bit
This bit is reserved in the ATmega103(L). Warning: When writing ADCSR, a logical “0”
must be written to this bit.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion is complete and the result is written to the
ADC Data Registers are updated. The ADC Conversion Complete interrupt is executed
if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by
writing a logical “1” to the flag. Beware that if doing a Read-Modify-Write on ADCSR, a
pending interrupt can be disabled. This also applies if the SBI and CBI instructions are
used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-
plete interrupt is activated.
• Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input
clock to the ADC.
Table 27. ADC Prescaler Selections
ADPS2
ADPS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Bit
15
14
13
$05 ($25)
$04 ($24)
ADC7
ADC6
ADC5
7
6
5
Read/Write
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
When an ADC conversion is complete, the result is found in these two registers. It is
essential that both registers are read and that ADCL is read before ADCH.
ATmega103(L)
ADPS0
Division Factor
0
Invalid
1
2
0
4
1
8
0
16
1
32
0
64
1
128
12
11
10
9
ADC9
ADC8
ADC4
ADC3
ADC2
ADC1
ADC0
4
3
2
1
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
8
ADCH
ADCL
0
R
R
0
0
81