IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 

Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 84/141

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Interface to External
SRAM
ATmega103(L)
84
The interface to the SRAM consists of:
Port A: multiplexed low-order address bus and data bus
Port C: high-order address bus
The ALE pin: address latch enable
The RD and WR pin: read and write strobes
The external data SRAM is enabled by setting the external SRAM enable bit (SRE) of
the MCU Control Register (MCUCR) and will override the setting of the Data Direction
Register (DDRA). When the SRE bit is cleared (zero), the external data SRAM is dis-
abled and the normal pin and data direction settings are used. When SRE is cleared
(zero), the address space above the internal SRAM boundary is not mapped into the
internal SRAM as AVR parts do not have an interface to the external SRAM.
When ALE goes from high to low, there is a valid address on Port A. ALE is low during a
data transfer. RD and WR are active when accessing the external SRAM only.
When the external SRAM is enabled, the ALE signal may have short pulses when
accessing the internal RAM, but the ALE signal is stable when accessing the external
SRAM.
Figure 50 shows how to connect an external SRAM to the AVR using eight latches that
are transparent when G is high.
By default, the external SRAM access is a three-cycle scheme as depicted in Figure 51.
When one extra wait state is needed in the access cycle, set the SRW bit (one) in the
MCUCR Register. The resulting access scheme is shown in Figure 52. In both cases,
note that Port A is data bus in one cycle only. As soon as the data access finishes, Port
A becomes a low-order address bus again.
Note:
If a read is followed by a write, or vice versa, there is no extra insertion of wait states in
between. The user may insert a NOP between consecutive read and write operations to
the external RAM, because such short time for releasing the bus is difficult to obtain with-
out making bus contention.
For details on the timing for the SRAM interface, please refer to Figure 79, Table 45,
Table 46, Table 47, and Table 48 in the section “DC Characteristics” on page 118 and
refer to “Architectural Overview” on page 8 for a description of the memory map, includ-
ing address space for SRAM.
Figure 50. External SRAM Connected to the AVR
Port A
ALE
AVR
Port C
RD
WR
D[7:0]
A[7:0]
D
Q
G
SRAM
A[15:8]
RD
WR
0945I–AVR–02/07