IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Port B Data Register – PORTB
Port B Data Direction Register
– DDRB
Port B Input Pins Address –
PINB
Port B as General Digital I/O
ATmega103(L)
88
inputs and are externally pulled low, they will source current if the internal pull-up resis-
tors are activated.
The Port B pins with alternate functions are shown in Table 29.
Table 29. Port B Pin Alternate Functions
Port Pin
Alternate Functions
PB0
SS (SPI Slave Select input)
PB1
SCK (SPI Bus Serial Clock)
PB2
MOSI (SPI Bus Master Output/Slave Input)
PB3
MISO (SPI Bus Master Input/Slave Output)
PB4
OC0/PWM0 (Output Compare and PWM Output for Timer/Counter0)
PB5
OC1A/PWM1A (Output Compare and PWM Output A for Timer/Counter1)
PB6
OC1B/PWM1B (Output Compare and PWM Output B for Timer/Counter1)
PB7
OC2/PWM2 (Output Compare and PWM Output for Timer/Counter2)
When the pins are used for the alternate function, the DDRB and PORTB Registers
have to be set according to the alternate function description.
Bit
7
6
5
$18 ($38)
PORTB7
PORTB6
PORTB5
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
Bit
7
6
5
$17 ($37)
DDB7
DDB6
DDB5
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
Bit
7
6
5
$16 ($36)
PINB7
PINB6
PINB5
Read/Write
R
R
R
Initial Value
N/A
N/A
N/A
The Port B Input Pins address (PINB) is not a register; this address enables access to
the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is
read and when reading PINB, the logical values present on the pins are read.
All eight pins in Port B have equal functionality when used as digital I/O pins.
PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this
pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero),
PBn is configured as an input pin. If PORTBn is set (one) when the pin configured as an
input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the
PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The
port pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
4
3
2
1
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
R/W
R/W
R/W
R/W
0
0
0
0
4
3
2
1
DDB4
DDB3
DDB2
DDB1
R/W
R/W
R/W
R/W
0
0
0
0
4
3
2
1
PINB4
PINB3
PINB2
PINB1
R
R
R
R
N/A
N/A
N/A
N/A
0
PORTB
R/W
0
0
DDB0
DDRB
R/W
0
0
PINB0
PINB
R
N/A
0945I–AVR–02/07