IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Alternate Functions of Port B
0945I–AVR–02/07
Table 30. DDBn Effects on Port B Pins
DDBn
PORTBn
I/O
0
0
Input
0
1
Input
1
0
Output
1
1
Output
Note:
n: 7,6...0, pin number
The alternate pin configuration is as follows:
• OC2/PWM2, Bit 7
OC2/PWM2, Output Compare output for Timer/Counter2 or PWM output when
Timer/Counter2 is in PWM mode. The pin has to be configured as an output to serve
this function.
• OC1B/PWM1B, Bit 6
OC1B/PWM1B, Output Compare output B for Timer/Counter1 or PWM output B when
Timer/Counter1 is in PWM mode. The pin has to be configured as an output to serve
this function.
• OC1A/PWM1A, Bit 5
OC1A/PWM1A, Output Compare output A for Timer/Counter1 or PWM output A when
Timer/Counter1 is in PWM mode. The pin has to be configured as an output to serve
this function.
• OC0/PWM0, Bit 4
OC0/PWM0, Output Compare output for Timer/Counter0 or PWM output when
Timer/Counter0 is in PWM mode. The pin has to be configured as an output to serve
this function.
• MISO – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a Master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit. See the description of the SPI port for further details.
• MOSI – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit. See the description of the SPI port for further details.
• SCK – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
ATmega103(L)
Pull-up
Comment
No
Tri-state (high-Z)
Yes
PBn will source current if ext. pulled low
No
Push-pull Zero Output
No
Push-pull One Output
89