ATMEGA103L-4AC Atmel, ATMEGA103L-4AC Datasheet - Page 80

IC MCU 128K 4MHZ A/D LV 64TQFP

ATMEGA103L-4AC

Manufacturer Part Number
ATMEGA103L-4AC
Description
IC MCU 128K 4MHZ A/D LV 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA103L-4AC

Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
ADC Noise Canceler
Function
ADC Multiplexer Select
Register – ADMUX
ADC Control and Status
Register – ADCSR
80
ATmega103(L)
The ADC features a noise canceler that enables conversion during Idle mode to reduce
noise induced from the CPU core. To make use of this feature, the following procedure
should be used:
1. Turn off the ADC by clearing ADEN.
2. Turn on the ADC and simultaneously start a conversion by setting ADEN and
3. Within 14 ADC clock cycles, enter Idle mode.
4. If no other interrupts occur before the ADC conversion completes, the ADC inter-
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
• Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2 - 0
The value of these three bits selects which analog input 7 - 0 is connected to the ADC.
• Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is
turned off. Turning the ADC off while a conversion is in progress will terminate this
conversion.
• Bit 6 – ADSC: ADC Start Conversion
A logical “1” must be written to this bit to start each conversion. The first time ADSC has
been written after the ADC has been enabled, or if ADSC is written at the same time as
the ADC is enabled, a dummy conversion will precede the initiated conversion. This
dummy conversion performs initialization of the ADC.
ADSC remains high during the conversion. ADSC goes low after the conversion is com-
plete, but before the result is written to the ADC Data Registers. This allows a new
conversion to be initiated before the current conversion is complete. The new conver-
sion will then start immediately after the current conversion completes. When a dummy
conversion precedes a real conversion, ADSC will stay high until the real conversion
completes.
Writing a zero to this bit has no effect.
Bit
$07 ($27)
Read/Write
Initial Value
Bit
$06 ($26)
Read/Write
Initial Value
ADSC. This starts a dummy conversion that will be followed by a valid
conversion.
rupt will wake up the MCU and execute the ADC conversion complete interrupt
routine.
ADEN
R/W
R
7
0
7
0
ADSC
R/W
R
6
0
6
0
R
5
0
R
5
0
ADIF
R/W
R
4
0
4
0
ADIE
R/W
R
3
0
3
0
MUX2
ADPS2
R/W
R/W
2
0
2
0
MUX1
R/W
ADPS1
1
0
R/W
1
0
MUX0
R/W
ADPS0
0
0
R/W
0
0
0945I–AVR–02/07
ADMUX
ADCSR

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