ATMEGA103L-4AC Atmel, ATMEGA103L-4AC Datasheet - Page 89

• Manufacturer Part Number: ATMEGA103L-4AC
• Description: IC MCU 128K 4MHZ A/D LV 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA103L-4AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Alternate Functions of Port B
0945I–AVR–02/07
Table 30. DDBn Effects on Port B Pins
Note:
The alternate pin configuration is as follows:
• OC2/PWM2, Bit 7
OC2/PWM2, Output Compare output for Timer/Counter2 or PWM output when
Timer/Counter2 is in PWM mode. The pin has to be configured as an output to serve
this function.
• OC1B/PWM1B, Bit 6
OC1B/PWM1B, Output Compare output B for Timer/Counter1 or PWM output B when
Timer/Counter1 is in PWM mode. The pin has to be configured as an output to serve
this function.
• OC1A/PWM1A, Bit 5
OC1A/PWM1A, Output Compare output A for Timer/Counter1 or PWM output A when
Timer/Counter1 is in PWM mode. The pin has to be configured as an output to serve
this function.
• OC0/PWM0, Bit 4
OC0/PWM0, Output Compare output for Timer/Counter0 or PWM output when
Timer/Counter0 is in PWM mode. The pin has to be configured as an output to serve
this function.
• MISO – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a Master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit. See the description of the SPI port for further details.
• MOSI – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit. See the description of the SPI port for further details.
• SCK – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDBn
0
0
1
1
n: 7,6...0, pin number
PORTBn
0
1
0
1
Output
Output
Input
Input
I/O
Pull-up
Yes
No
No
No
Comment
Tri-state (high-Z)
PBn will source current if ext. pulled low
Push-pull Zero Output
Push-pull One Output
ATmega103(L)
89