ATMEGA103L-4AI Atmel, ATMEGA103L-4AI Datasheet - Page 52

• Manufacturer Part Number: ATMEGA103L-4AI
• Description: IC MCU 128K 4MHZ A/D LV 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA103L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer/Counter1 Output
Compare Register – OCR1AH
and OCR1AL
Timer/Counter1 Output
Compare Register – OCR1BH
and OCR1BL
Timer/Counter1 Input Capture
Register – ICR1H and ICR1L
52
ATmega103(L)
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read
and write access. If Timer/Counter1 is written to and a clock source is selected, the
Timer/Counter1 continues counting in the clock cycle after it is preset with the written
value.
The Output Compare Registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously
compared with Timer/Counter1. Actions on compare matches are specified in the
Timer/Counter1 Control and Status Registers. A compare match occurs only if
Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A
or OCR1B to the same value does not generate a compare match.
A compare match will set the Compare Interrupt Flag in the CPU clock cycle following
the compare event.
Since the Output Compare Registers (OCR1A and OCR1B) are 16-bit registers, a tem-
porary register TEMP is used when OCR1A/B are written to ensure that both bytes are
updated simultaneously. When the CPU writes the High Byte, OCR1AH or OCR1BH,
the data is temporarily stored in the TEMP Register. When the CPU writes the Low Byte,
OCR1AL or OCR1BL, the TEMP Register is simultaneously written to OCR1AH or
OCR1BH. Consequently, the High Byte OCR1AH or OCR1BH must be written first for a
full 16-bit register write operation.
The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program
and interrupt routines perform access to registers using TEMP, interrupts must be dis-
abled during access from the main program.
Bit
$2B
$2A
Read/Write
Initial Value
Bit
$29
$28
Read/Write
Initial Value
Bit
$27 ($37)
$26 ($36)
full 16-bit register read operation. When using Timer/Counter1 as an 8-bit Timer, it
is sufficient to read the Low Byte only.
MSB
MSB
MSB
R/W
R/W
R/W
R/W
15
15
15
7
0
0
7
0
0
7
R/W
R/W
R/W
R/W
14
14
14
6
0
0
6
0
0
6
R/W
R/W
R/W
R/W
13
13
13
5
0
0
5
0
0
5
R/W
R/W
R/W
R/W
12
12
12
4
0
0
4
0
0
4
R/W
R/W
R/W
R/W
11
11
11
3
0
0
3
0
0
3
R/W
R/W
R/W
R/W
10
10
10
2
0
0
2
0
0
2
R/W
R/W
R/W
R/W
9
1
0
0
9
1
0
0
9
1
LSB
R/W
R/W
LSB
R/W
R/W
LSB
8
0
0
0
8
0
0
0
8
0
0945I–AVR–02/07
OCR1AH
OCR1AL
OCR1BH
OCR1BL
ICR1H
ICR1L