ATMEGA103L-4AI Atmel, ATMEGA103L-4AI Datasheet - Page 70

IC MCU 128K 4MHZ A/D LV 64TQFP

ATMEGA103L-4AI

Manufacturer Part Number
ATMEGA103L-4AI
Description
IC MCU 128K 4MHZ A/D LV 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA103L-4AI

Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
UART Control
UART I/O Data Register – UDR
UART Status Register – USR
70
ATmega103(L)
The UDR Register is actually two physically separate registers sharing the same I/O
address. When writing to the register, the UART Transmit Data Register is written.
When reading from UDR, the UART Receive Data Register is read.
The USR Register is a read-only register providing information on the UART Status.
• Bit 7 – RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift
Register to UDR. The bit is set regardless of any detected framing errors. When the
RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when
RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception
is used, the UART Receive Complete Interrupt routine must read UDR in order to clear
RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
• Bit 6 – TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit
Shift Register has been shifted out and no new data has been written to the UDR. This
flag is especially useful in half-duplex communications interfaces, where a transmitting
application must enter Receive mode and free the communications bus immediately
after completing the transmission.
When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete
interrupt to be executed. TXC is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical
“1” to the bit.
• Bit 5 – UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is transferred to the Transmit Shift
Register. Setting of this bit indicates that the Transmitter is ready to receive a new char-
acter for transmission.
When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be exe-
cuted as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven
data transmittal is used, the UART Data Register Empty Interrupt routine must write
UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou-
tine terminates.
UDRE is set (one) during reset to indicate that the Transmitter is ready.
Bit
$0C ($2C)
Read/Write
Initial Value
Bit
$0B ($2B)
Read/Write
Initial Value
MSB
RXC
R/W
R
7
0
7
0
R/W
TXC
R/W
6
0
6
0
UDRE
R/W
R
5
0
5
1
R/W
FE
R
4
0
4
0
R/W
OR
R
3
0
3
0
R/W
R
2
0
2
0
R/W
R
1
0
1
0
LSB
R/W
R
0
0
0
0
0945I–AVR–02/07
UDR
USR

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