AT89S8252-24JI Atmel, AT89S8252-24JI Datasheet

MCU W/SPI 8KB FLSH 2K EEP 44PLCC

AT89S8252-24JI

Manufacturer Part Number
AT89S8252-24JI
Description
MCU W/SPI 8KB FLSH 2K EEP 44PLCC
Manufacturer
Atmel
Series
89Sr
Datasheet

Specifications of AT89S8252-24JI

Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Other names
AT89S825224JI

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Features
Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcontroller with 8K
bytes of downloadable Flash programmable and erasable read-only memory and 2K
bytes of EEPROM. The device is manufactured using Atmel’s high-density nonvolatile
memory technology and is compatible with the industry-standard 80C51 instruction
set and pinout. The on-chip downloadable Flash allows the program memory to be
reprogrammed In-System through an SPI serial interface or by a conventional nonvol-
atile memory programmer. By combining a versatile 8-bit CPU with downloadable
Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcontroller, which
provides a highly-flexible and cost-effective solution to many embedded control
applications.
The AT89S8252 provides the following standard features: 8K bytes of downloadable
Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog
timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89S8252 is designed with static logic for operation down to zero frequency and
supports two software selectable power saving modes. The Idle Mode stops the CPU
while allowing the RAM, timer/counters, serial port, and interrupt system to continue
functioning. The Power-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next external interrupt or hardware reset.
The downloadable Flash can be changed a single byte at a time and is accessible
through the SPI serial interface. Holding RESET active forces the SPI bus into a serial
programming interface and allows the program memory to be written to or read from
unless lock bits have been activated.
Compatible with MCS
8K Bytes of In-System Reprogrammable Downloadable Flash Memory
2K Bytes EEPROM
4V to 6V Operating Range
Fully Static Operation: 0 Hz to 24 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Nine Interrupt Sources
Programmable UART Serial Channel
SPI Serial Interface
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down
Programmable Watchdog Timer
Dual Data Pointer
Power-off Flag
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
– Endurance: 100,000 Write/Erase Cycles
®
51 Products
8-bit
Microcontroller
with 8K Bytes
Flash
AT89S8252
Not Recommended
for New Designs.
Use AT89S8253.
0401G–MICRO–3/06
1

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AT89S8252-24JI Summary of contents

Page 1

... In addition, the AT89S8252 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning ...

Page 2

... P2.4 (A12) (RD) P3 P2.3 (A11) XTAL2 18 23 P2.2 (A10) XTAL1 19 22 P2.1 (A9) GND 20 21 P2.0 (A8) Pin Description VCC GND Port 0 Port 1 AT89S8252 2 PLCC (MOSI) P1.5 7 (MISO) P1.6 8 (SCK) P1.7 9 RST 10 (RXD) P3 (TXD) P3.1 13 (INT0) P3.2 14 (INT1) P3.3 15 (T0) P3.4 16 (T1) P3.5 17 Supply voltage ...

Page 3

... PORT 0 DRIVERS PORT 0 RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 3 DOG LATCH PORT 3 DRIVERS P3.0 - P3.7 AT89S8252 P2.0 - P2.7 PORT 2 DRIVERS PORT 2 FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL ...

Page 4

... As inputs, Port 3 pins that are exter- nally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S8252, as shown in the following table. ) because of the internal pull-ups. ...

Page 5

... Program Store Enable is the read strobe to external program memory. When the AT89S8252 is executing code from external program memory, PSEN is acti- vated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. ...

Page 6

... Special Function Registers Table 1. AT89S8252 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 T2CON T2MOD 0C8H 00000000 XXXXXX00 0C0H IP 0B8H XX000000 P3 0B0H 11111111 IE 0A8H 0X000000 P2 0A0H 11111111 SCON SBUF 98H 00000000 XXXXXXXX P1 90H ...

Page 7

... Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. 0401G–MICRO–3/06 RCLK TCLK EXEN2 AT89S8252 Reset Value = 0000 0000B TR2 C/T2 CP/RL2 ...

Page 8

... RDY/BSY = 1 means that the EEPROM is ready to be programmed. While programming operations are being executed, the RDY/BSY bit equals “0” and is automatically reset to “1” when programming is completed. WDTEN Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer. AT89S8252 8 PS0 EEMWE ...

Page 9

... Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by RESET. DORD MSTR CPOL divided by OSC. AT89S8252 Reset Value = 0000 01XXB CPHA SPR1 SPR0 follows: OSC. 9 ...

Page 10

... The AT89S8252 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. ...

Page 11

... Timer 0 and Timer 1 in the AT89S8252 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, refer to the Atmel web site (http://www.atmel.com). From the home page, select “Products”, then “ ...

Page 12

... T2 PIN TRANSITION DETECTOR T2EX PIN AT89S8252 12 Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 tran- sition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle ...

Page 13

... RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. AT89S8252 13 ...

Page 14

... Symbol Function – Not implemented, reserved for future use. T2OE Timer 2 Output Enable bit. DCEN When set, this bit allows Timer configured as an up/down counter. Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) AT89S8252 14 – – – Reset Value = XXXX XX00B – T2OE ...

Page 15

... As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below. Modes 1 and 3 -------------------------------------- - = Baud Rate where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. AT89S8252 TIMER 1 OVERFLOW ÷ 2 "0" "1" SMOD1 "1" "0" ...

Page 16

... Programmable Clock Out AT89S8252 16 Timer baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not gener- ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2) ...

Page 17

... SPI CONTROL SPI STATUS REGISTER 0401G–MICRO–3/06 MSB LSB 8/16-BIT SHIFT REGISTER READ DATA BUFFER CLOCK SPI CLOCK (MASTER) CLOCK LOGIC MSTR SPE 8 SPI CONTROL REGISTER 8 8 SPI INTERRUPT INTERNAL REQUEST DATA BUS AT89S8252 S MISO P1.6 M MOSI M P1.5 S SCK S 1 P1.4 17 ...

Page 18

... CLOCK GENERATOR AT89S8252 18 The UART in the AT89S8252 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the Atmel web site (http://www.atmel.com). From the home page, select “Products”, then “Microcontrollers, then “8051-Architecture”. Click on “Documentation”, then on “Other Documents”. Open the document “ ...

Page 19

... MSB The AT89S8252 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once ...

Page 20

... IE.2 ET0 IE.1 EX0 IE.0 User software should never write 1s to unimplemented bits, because they may be used in future AT89 products. Figure 10. Interrupt Sources AT89S8252 20 ET2 ES ET1 Function Disables all interrupts interrupt is acknowledged each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ...

Page 21

... Figure 12. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 11. Oscillator Connections Note: C1 ± for Crystals = 40 pF ± for Ceramic Resonators Figure 12. External Clock Drive Configuration AT89S8252 21 ...

Page 22

... The interrupt service routine starts (nominal) after the enabled interrupt pin is activated. The AT89S8252 has three lock bits that can be left unprogrammed (U) or can be pro- grammed (P) to obtain the additional features listed in the following table. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched dur- ing reset ...

Page 23

... Code array and 2000H to 27FFH for the Data array. The Code and Data memory arrays on the AT89S8252 are programmed byte-by-byte in either programming mode. An auto-erase cycle is provided with the self-timed program- ming operation in the serial programming mode. There is no need to perform the Chip Erase operation to reprogram any memory location in the serial programming mode unless any of the lock bits have been programmed ...

Page 24

... Chip Erase operation first to erase both arrays. Data Polling: The AT89S8252 features DATA Polling to indicate the end of a byte write cycle. During a byte write cycle in the parallel or serial programming mode, an attempted read of the last byte written will result in the complement of the written datum on P0 ...

Page 25

... XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/40 of the crystal frequency. With a 24 MHz oscillator clock, the maximum SCK frequency is 600 kHz. To program and verify the AT89S8252 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to “ ...

Page 26

... DATA polling is used to indicate the end of a byte write cycle which typically takes less than 2 5V. 2. “aaaaa” = high order address. 3. “x” = don’t care. AT89S8252 26 The Instruction Set for Serial Programming follows a 3-byte protocol and is shown in the following table: ...

Page 27

... RST PSEN ALE/PROG EA/V PP ( 12V H L 12V 12V H L 12V 12V 12V 12V ( 12V ( 12V 12V AT89S8252 Data I/O P2.6 P2.7 P3.6 P3.7 P0.7 DIN DOUT DIN DOUT @P0.2 @P0.1 @P0 DOUT DOUT ...

Page 28

... Figure 14. Verifying the Flash/EEPROM Memory AT89S8252 ADDR. P1 0000H/2FFFH P2 A13 P2.6 SEE FLASH P2.7 PROGRAMMING P3.6 MODES TABLE P3.7 XTAL2 3-24 Mhz XTAL1 GND AT89S8252 28 Figure 15. Flash/EEPROM Serial Downloading + PGM P0 DATA INSTRUCTION ALE PROG DATA OUTPUT 3-24 MHz P3.4 RDY/ BSY ...

Page 29

... ENABLE Low to Data Valid ELQV t Data Float after ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC Flash/EEPROM Programming and Verification Waveforms – Parallel Mode 0401G–MICRO–3/06 PP AT89S8252 Min Max Units 11.5 12 MHz 48t CLCL 48t ...

Page 30

... Parameter 1/t Oscillator Frequency CLCL t Oscillator Period CLCL t SCK Pulse Width High SHSL t SCK Pulse Width Low SLSH t MOSI Setup to SCK High OVSH t MOSI Hold after SCK High SHOX AT89S8252 MSB MSB t t OVSH SHOX SCK t SHSL = -40°C to 85° Min 0 41 ...

Page 31

... OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89S8252 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...

Page 32

... AVDV t ALE Low Low LLWL t Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold after WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89S8252 32 Variable Oscillator Min Max CLCL CLCL CLCL CLCL CLCL ...

Page 33

... External Program Memory Read Cycle External Data Memory Read Cycle 0401G–MICRO–3/06 AT89S8252 33 ...

Page 34

... External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89S8252 4.0V to 6.0V CC Min Max Units MHz 0401G–MICRO–3/06 ...

Page 35

... For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V 0401G–MICRO–3/ and Load Capacitance = 80 pF. CC ( level occurs AT89S8252 Variable Oscillator Min Max 12t CLCL 10t - 133 CLCL 2t - 117 CLCL ...

Page 36

... AT89S8252 36 AT89S8252 TYPICAL ICC (ACTIVE) at 25° (MHz) AT89S8252 TYPICAL ICC (IDLE) at 25°C 4.8 4 2.4 m 1.6 A 0.8 0 (MHz) Notes: 1. XTAL1 tied to GND for Icc (power-down) 2. Lock bits programmed 0401G–MICRO–3/06 ...

Page 37

... Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 0401G–MICRO–3/06 Ordering Code AT89S8252-24AC AT89S8252-24JC AT89S8252-24PC AT89S8252-24AI AT89S8252-24JI AT89S8252-24PI Package Type AT89S8252 Package Operation Range 44A Commercial 44J (0°C to 70°C) 40P6 ...

Page 38

... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89S8252 TITLE 44A, 44-lead Body Size, 1 ...

Page 39

... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 0401G–MICRO–3/06 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89S8252 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...

Page 40

... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89S8252 40 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600" ...

Page 41

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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