IC MICRO CTRL 64K FLASH 44PLCC

T89C51RD2-SLSIM

Manufacturer Part NumberT89C51RD2-SLSIM
DescriptionIC MICRO CTRL 64K FLASH 44PLCC
ManufacturerAtmel
Series89C
T89C51RD2-SLSIM datasheet
 


Specifications of T89C51RD2-SLSIM

Core Processor8051Core Size8-Bit
Speed40MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Eeprom Size2K x 8Ram Size1.25K x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case44-PLCC
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantData Converters-
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Features
80C52 Compatible
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports (or 6 in 64/68 Pins Packages)
– Three 16-bit Timer/Counters
– 256 bytes Scratch Pad RAM
– 7 Interrupt Sources With 4 Priority Levels
ISP (In-System Programming) Using Standard V
Boot Flash Contains Low Level Flash Programming Routines and a Default Serial
Loader
High-Speed Architecture
– 40 MHz in Standard Mode
– 20 MHz in X2 Mode (6 Clocks/Machine Cycle)
64K bytes On-chip Flash Program/Data Memory
– Byte and Page (128 bytes) Erase and Write
– 100K Write Cycles
On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 bytes)
– 768 Bytes Selected at Reset for T87C51RD2 Compatibility
Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independant Selection for CPU and Each Peripheral
2K bytes EEPROM Block for Data Storage
– 100K Write Cycle
Programmable Counter Array with
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
Watchdog Timer Capabilities
Asynchronous Port Reset
Full-duplex Enhanced UART
Low EMI (Inhibit ALE)
– Hardware Watchdog Timer (One-time Enabled with Reset-out)
Power Control Modes:
– Idle Mode
– Power-down Mode
Power Supply:
– M version: Commercial and Industrial
4.5V to 5.5V: 40 MHz (X1 Mode), 20 MHz (X2 Mode)
3V to 5.5V: 33 MHz (X1 Mode), 16 MHz (X2 Mode)
– L version: Commercial and industrial
2.7V to 3.6V: 25 MHz (X1 Mode), 12 MHz (X2 Mode)
Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40 to +85°C)
Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64
Power Supply
CC
0 to 40 MHz
Flash
Programmable
8-bit
Microcontroller
T89C51RD2
Rev. 4243G–8051–05/03
1

T89C51RD2-SLSIM Summary of contents

  • Page 1

    ... MHz (X1 Mode), 16 MHz (X2 Mode) – L version: Commercial and industrial 2.7V to 3.6V: 25 MHz (X1 Mode), 12 MHz (X2 Mode) • Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40 to +85°C) • Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64 Power Supply MHz Flash Programmable 8-bit Microcontroller T89C51RD2 Rev. 4243G–8051–05/03 1 ...

  • Page 2

    ... V pin. CC The T89C51RD2 retains all features of the ATMEL 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters. In addition, the T89C51RD2 has a Programmable Counter Array, an XRAM of 1024 bytes, an EEPROM of 2048 bytes, a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improve- ment mechanism (X2 mode) ...

  • Page 3

    ... Flash RAM EUART 64Kx8 256x8 C51 CORE IB-bus CPU Timer 0 Parallel I/O Ports & Ext. Bus INT Ctrl Timer 1 Port 0Port 1 Port 2 Port 3 (3) (3) (3) (3) T89C51RD2 (1) (1) (1) (1) XRAM EEPROM PCA Timer2 1Kx8 2Kx8 Watch Dog Port 4 Port 5 (2) (2) 3 ...

  • Page 4

    ... P3.0/RxD 10 PDIL P3.1/TxD 11 12 P3.2/INT0 P3.3/INT1 13 P3.4/ P3.5/T1 16 P3.6/WR 17 P3.7/RD 18 XTAL2 19 XTAL1 20 VSS P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 T89C51RD2 4 40 VCC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 P0.3/AD3 36 P0.4/AD4 35 P0.5/AD5 34 P0.6/AD6 33 P1.5/CEX2 7 P0.7/AD7 32 P1.6/CEX3 P1.7/CEx4 9 ALE/PROG 30 RST 10 PSEN 29 P3 ...

  • Page 5

    ... P1.3/CEX0 23 P4.1 24 P1.4/CEX1 25 P4 P2.4/A12 48 P2.3/A11 47 P4.7 46 P2.2/A10 45 P2.1/A9 44 P2.0/ NIC 40 VSS 39 P4.5 38 XTAL1 XTAL2 37 P3.7/RD 36 P4.4 35 P3.6/ T89C51RD2 PLCC 68 PLCC68 P5.0 59 P2.4/A12 58 P2.3/A11 57 P4.7 56 P2.2/A10 55 P2.1/A9 54 P2.0/A8 P4.6 53 NIC 52 VSS 51 50 P4.5 49 XTAL1 48 XTAL2 47 P3.7/RD 46 P4.4 45 P3.6/ ...

  • Page 6

    ... P2.0-P2.7 21-28 24-31 P3.0-P3.7 10-17 11, 13- T89C51RD2 6 Type Name and Function 16 I Ground: 0V reference 39 I Optional Ground: Contact the Sales Office for ground connection. Power Supply: This is the power supply voltage for normal, idle and power-down 38 I operation 37-30 I/O Port 0: Port open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs ...

  • Page 7

    ... EA will be internally latched on Reset Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits Crystal 2: Output from the inverting oscillator amplifier T89C51RD2 permits a power-on reset using only This pin is an output when the hardware watchdog forces ...

  • Page 8

    ... SFR Mapping T89C51RD2 8 The Special Function Registers (SFRs) of the T89C51RD2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3, P4, P5 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...

  • Page 9

    ... AUXR1 XXXX 00X0 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C T89C51RD2 5/D 6/E 7/F CCAP3H CCAP4H XXXX XXXX XXXX XXXX CCAP3L CCAP4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 X000 0000 ...

  • Page 10

    ... The ALE disabling • Some enhanced features are also located in the UART and the Timer 2 The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...

  • Page 11

    ... Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) 3 T2X2 Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. T89C51RD2 STD Mode SiX2 T2X2 ...

  • Page 12

    ... T89C51RD2 12 Bit Bit Number Mnemonic Description Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) 2 T1X2 Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle Timer0 clock (This control bit is validated when the CPU clock X2 is set ...

  • Page 13

    ... In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 2. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3. T89C51RD2 External Data Memory - - ...

  • Page 14

    ... Application T89C51RD2 14 Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destina- tion" ...

  • Page 15

    ... Table 6. Table 6. Description of Expanded RAM Port XRAM size T89C51RD2 1024 The T89C51RD2 has internal data memory that is mapped into four separate segments. The four segments are: • 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. • ...

  • Page 16

    ... T89C51RD2 16 • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). • The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions ...

  • Page 17

    ... User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. T89C51RD2 - M0 - ...

  • Page 18

    ... Auto-Reload Mode T89C51RD2 18 The timer 2 in the T89C51RD2 is compatible with the timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade controlled by T2CON register (See Table 8) and T2MOD register (See Table 9). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 ...

  • Page 19

    ... To start the timer, set TR2 run control bit in T2CON register possible to use timer baud rate generator and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. T89C51RD2 0 1 TR2 ...

  • Page 20

    ... Figure 6. Clock-Out Mode C/ XTAL1 T2 T2EX T89C51RD2 20 :2 TR2 T2CON reg TL2 (8-bit) RCAP2L (8-bit) Toggle Q D T2OE T2MOD reg EXF2 T2CON reg EXEN2 T2CON reg TH2 (8-bit) OVEFLOW RCAP2H (8-bit) TIMER 2 INTERRUPT 4243G–8051–05/03 ...

  • Page 21

    ... Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. 0 CP/RL2# Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable T89C51RD2 TCLK EXEN2 TR2 C/T2# OSC 1 ...

  • Page 22

    ... T89C51RD2 22 Table 9. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...

  • Page 23

    ... X2 Mode) • 1/4 the oscillator frequency. (Or 1 Mode) • The Timer 0 overflow • The input on the ECI pin (P1.2) T89C51RD2 mode) External I/O Pin P1.2 / ECI P1.3 / CEX0 P1.4 / CEX1 P1.5 / CEX2 P1.6 / CEX3 P1.7 / CEX4 ...

  • Page 24

    ... Figure 7. PCA Timer/Counter Fosc /12 Fosc / 4 T0 OVF P1.2 Idle T89C51RD2 24 CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 Table 10. CMOD: PCA Counter Mode Register CMOD CIDL Address 0D9H Reset value 0 Symbol Function Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during CIDL idle Mode ...

  • Page 25

    ... User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. The watchdog timer function is implemented in module 4 (See Figure 10). T89C51RD2 CR - CCF4 CCF3 ...

  • Page 26

    ... Figure 8. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 ECF T89C51RD2 26 The PCA interrupt system is shown in Figure CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn.0 PCA Modules: each one of the five compare/capture modules has six possible func- tions. It can perform: • ...

  • Page 27

    ... The value read from a reserved bit is indeterminate. Table 13. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn T89C51RD2 ECO CAPP CAPN - MATn (1) TOGn PWMm ECCFn Module Function Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger CEXn ...

  • Page 28

    ... T89C51RD2 28 ECOMn CAPPn CAPNn MATn TOGn There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 14 & ...

  • Page 29

    ... CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 10). T89C51RD2 CCON 0xD8 ...

  • Page 30

    ... Figure 10. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable Only for Module 4 High Speed Output Mode T89C51RD2 30 CCF4 CF CR CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen ...

  • Page 31

    ... CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. T89C51RD2 CCON 0xD8 PCA IT ...

  • Page 32

    ... PCA Watchdog Timer T89C51RD2 32 Figure 12. PCA PWM Mode Overflow Enable ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge ...

  • Page 33

    ... Serial I/O Port Framing Error Detection 4243G–8051–05/03 The serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul- ...

  • Page 34

    ... Automatic Address Recognition Given Address T89C51RD2 34 Figure 15. UART Timings in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame ...

  • Page 35

    ... XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. Table 18. SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable T89C51RD2 ...

  • Page 36

    ... T89C51RD2 36 Table 19. SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable Table 20. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. ...

  • Page 37

    ... Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. T89C51RD2 POF GF1 GF0 ...

  • Page 38

    ... RI TI TF2 EXF2 Individual Enable T89C51RD2 38 The T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA glo- bal interrupt. These interrupts are shown in Figure 16. IPH ...

  • Page 39

    ... Timer 0 overflow interrupt Enable bit 1 ET0 Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit 0 EX0 Clear to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable T89C51RD2 ET1 EX1 ET0 1 0 EX0 39 ...

  • Page 40

    ... T89C51RD2 40 Table 24. IP Register IP - Interrupt Priority Register (B8h PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt priority bit 6 PPC Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit ...

  • Page 41

    ... PT0H External interrupt 0 Priority High bit PX0H PX0 PX0H Reset Value = X000 0000b Not bit addressable T89C51RD2 PSH PT1H PX1H Description Priority Level Lowest Highest Lowest Highest Priority Level Lowest Highest Lowest Highest Lowest Highest Priority Level Lowest Highest Priority Level ...

  • Page 42

    ... Cold Reset T89C51RD2 42 Two power reduction modes are implemented in the T89C51RD2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”. ...

  • Page 43

    ... Figure 18. Figure 18. Reset Circuitry for WDT Reset-out Usage VDD + RST VDD 1K RST VSS T89C51RD2 VDD Rise Time 10 ms 1.2 µF 3.9 µF starts from 0V to the nominal value. If the time between 2 VDD P VSS (1) 100 ms 12 µ ...

  • Page 44

    ... In this case, the higher priority interrupt service routine is exe- cuted. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that puts the T89C51RD2 into Power-down mode. can be lowered to save further CC 4243G– ...

  • Page 45

    ... PORT0 1 1 Port Data 1 1 Floating 0 0 Port Data 0 0 Floating Port 0 can force a 0 level. A "one" will leave port floating. T89C51RD2 Active Phase PORT1 PORT2 (1) Port Data Port Data Port Data Address (1) Port Data Port Data Port Data Port Data ...

  • Page 46

    ... Hardware Watchdog Timer Using the WDT T89C51RD2 46 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H ...

  • Page 47

    ... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the T89C51RD2 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...

  • Page 48

    ... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the T89C51RD2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 30. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...

  • Page 49

    ... XRAM size: Accessible size of the XRAM. Table 6. EXTRAM bit 1 EXTRAM See Table 6. ALE Output bit 0 AO Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. Reset Value = XX0X 1000b Not bit addressable T89C51RD2 XRS1 XRS0 EXTRAM Description 0 AO ...

  • Page 50

    ... EEPROM Data Memory General Description Write Data in the Column Latches Programming T89C51RD2 50 The EEPROM memory block contains 2048 bytes and is organized in 32 pages (or rows bytes. The necessary high programming voltage is generated on-chip using the standard Vcc pin of the microcontroller. The EEPROM memory block is located at the addresses 0000h to 07FFh of the XRAM memory space and is selected by setting control bits in the EECON register ...

  • Page 51

    ... In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Reset Value = XXXX XX00b T89C51RD2 EECON,#02h ; EEE=1 EEPROM mapped A,@DPTR ; Read data from EEPROM ...

  • Page 52

    ... T89C51RD2 52 Table 33. EETIM Register EETIM (S:0D3h) EEPROM timing Control Register Bit Bit Number Mnemonic Description Write Timer Register The write timer register value is required to adapt the write time to the oscillator frequency 7-0 EETIM Value = 5 * Fxtal (MHz) in normal mode Fxtal in X2 mode. ...

  • Page 53

    ... Second, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the Boot loader. • Third, the Flash may be programmed using the parallel method by using a conventional EPROM programmer. The parallel programming method used by T89C51RD2 pins of the CC supply. CC ...

  • Page 54

    ... Reset Value = xxxx 0000b The Flash programming application note and API source code are available on request. The only hardware register of the T89C51RD2 is called Hardware Security Byte (HSB). After full Flash erasure, the content of this byte is FFh; each bit is active at low level. ...

  • Page 55

    ... When this bit is set the boot address is 0000h. • When this bit is reset the boot address is FC03h. By default, this bit is cleared and the ISP is enabled. The three lock bits provide different levels of protection for the on-chip code and data, when programmed according to Table 29. T89C51RD2 ...

  • Page 56

    ... Default Values Software Registers T89C51RD2 56 Table 34. Program Lock bits Program Lock Bits Protection Description Security level LB0 LB1 LB2 No program lock features enabled. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled ...

  • Page 57

    ... Note: WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. T89C51RD2 Default Value FFh FCh 18h or 1Bh FFh ATMEL Wireless and 58h Microcontrollers D7h C51 X2, Electrically Erasable T89C51RD2 memories size FCh T89C51RD2 , revision 0 FFh and Table 30 Table 31 57 ...

  • Page 58

    ... FC00h Virgin Application 0000h Default After ISP T89C51RD2 58 T89C51RD2 parts are delivered in standard with the ISP boot in the Flash memory. After ISP or parallel programming, the possible contents of the Flash memory are sum- marized on the figure below: Boot Boot Virgin Application or appli ...

  • Page 59

    ... Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 22. Diagram Context Description Access via Specific Protocol Access From User Application ISP: In-system Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Bit T89C51RD2 Bootloader Flash Memory 59 ...

  • Page 60

    ... Functional Description Figure 23. Bootloader Functional Description Exernal Host with Specific Protocol Communication T89C51RD2 60 ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device ...

  • Page 61

    ... Note: The BLJB test is perform by hardware to prevent any program execution. The Software Boot Vector contains the high address of custumer bootloader stored in the application. SBV = FCh (default value custumer bootloader in user Flash. SBV Note: The custumer bootloader is called by LJMP [SBV]00h instruction. T89C51RD2 61 ...

  • Page 62

    ... Boot Process Figure 24. Bootloader Process JUMP to 0000h User Application T89C51RD2 62 RESET Yes (PSEN = and ALE = 1 or not connected) Hardware Condition? Yes BLJB = 1 ? JUMP to FC03h BSB=0 BSB = 00h ? SBV=FCh SBV = FCh ? SBV=XXh JUMP to XX00h User Boot Loader JUMP to FC00h Default Boot Loader ...

  • Page 63

    ... ASCII hexadecimal digits to one Byte of binary, and including the Reclen field to and including the last Byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. T89C51RD2 Record Type Data or Info 2 bytes ...

  • Page 64

    ... Functional Description Configuration and Manufacturer Information Software Security Bits (SSB) T89C51RD2 64 The table below lists Configuration and Manufacturer byte information used by the boot- loader. This information can be accessed through a set of API or ISP commands. Mnemonic Description BSB Boot Status Byte SBV Software Boot Vector ...

  • Page 65

    ... Read only access allowed Info Bootloader Info Read only access allowed Erase Block Allowed Full-chip Erase Allowed Blank Check Allowed T89C51RD2 Level 1 Level 2 Read only access allowed Read only access allowed Read only access allowed Read only access allowed Not allowed Not allowed Allowed ...

  • Page 66

    ... Full Chip Erase Checksum Error Flow Description Overview Communication Initialization T89C51RD2 66 The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some Bytes used by the bootloader at their default values: • BSB = FFh • SBV = FCh • ...

  • Page 67

    ... This information is then used to pro- gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the T89C51RD2 to establish the baud rate. Table 39 shows the autobaud capability. ...

  • Page 68

    ... Sends first character of the Frame Sends frame (made of 2 ASCII characters per Byte) Echo analysis Write/Program Commands T89C51RD2 68 All commands are sent using the same flow. Each frame sent by the host is echoed by the bootloader. ":" ":" This flow is common to the following frames: • ...

  • Page 69

    ... BOOTLOADER : 01 0010 Programming Atmel function (write SSB to level 2) HOST : 02 0000 BOOTLOADER : 02 0000 F5 Writing Frame (write BSB to 55h) HOST : 03 0000 BOOTLOADER : 03 0000 T89C51RD2 Bootloader Wait Write Command Checksum error Send Checksum error NO_SECURITY Send Security error Wait Programming Send COMMAND_OK 69 ...

  • Page 70

    ... OR Wait Checksum Error COMMAND ABORTED Wait COMMAND_OK OR COMMAND FINISHED Wait Address not erased COMMAND FINISHED Example T89C51RD2 70 Blank Check Command ’X’ & twice (CR & LF) ’.’ & CR & LF address & CR & LF Blank Check ok HOST : 05 0000 04 0000 7FFF 01 78 BOOTLOADER : 05 0000 04 0000 7FFF ...

  • Page 71

    ... Display Command ’X’ & twice (CR & LF) Send Checksum Error ’L’ & CR & LF Send Security Error "Address = " "Reading value" CR & LF T89C51RD2 Bootloader Wait Display Command Checksum error RD_WR_SECURITY Read Data All data read Complete Frame Send Display Data ...

  • Page 72

    ... Send Read Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Value of Data COMMAND FINISHED Example T89C51RD2 72 Display data from address 0000h to 0020h HOST : 05 0000 04 0000 0020 00 D7 BOOTLOADER : 05 0000 04 0000 0020 00 D7 BOOTLOADER 0000=-----data------ CR LF BOOTLOADER ...

  • Page 73

    ... API “PROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 Bytes in a sin- gle command. All routines for software access are provided in the C Flash driver available at Atmel’s web site. T89C51RD2 Data[0] Data[1] Command Effect Program Nb Data Byte. ...

  • Page 74

    ... PAGE 09h Byte to program READ BOOT ID1 0Eh XXh READ BOOT ID2 0Eh XXh READ BOOT VERSION 0Fh XXh T89C51RD2 74 The API calls description and arguments are shown in Table 41. DPTR0 DPTR1 ACC=Manufacturer 0000h XXh 0001h XXh ACC= Device ID 1 0002h XXh ...

  • Page 75

    ... As these registers can only be accessed by hardware, they must be read by the parallel programmers and then copied in the XAF in order to make their values accessible by software (ISP or API). In order to program and verify the Flash or to read the signature bytes, the T89C51RD2 is placed in specific set-up modes. (See Figure 31.) Figure 31. Set-Up Modes Configuration ...

  • Page 76

    ... PGXL (up to 128 bytes) Read Signature bytes 30h (Manufacturer code) TMS 31h (Device ID #1) 60h (Device ID #2) 61h (Device ID #3) RXAF Read Extra Memory (XAF) T89C51RD2 76 Control and program signals must be held at the levels indicated in the two following tables. Rst Psen ...

  • Page 77

    ... FF: test mode PGMS (din = FF). 4243G–8051–05/03 P1[7..0] P2[5..0] P3.0 P3 A7-A0 A13- A7-A0 A13- A7-A0 A13- A7- (0-7F) A7- (0-7F) 30h 31h 60h 61h Addr (0-7F) T89C51RD2 P3.2 P3.3 P3.4 P3 A14 A15 x 0 A14 A15 x 1 A14 A15 ...

  • Page 78

    ... Verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the T89C51RD2. P 2.7 is used to enable data output. To verify the T89C51RD2 code the following sequence must be exercised: • Step 1:Activate the combination of program and control signals (PGMV) • ...

  • Page 79

    ... Extra Memory Mapping 4243G–8051–05/03 Programming Cycle Data In 48 clk (load latch ) (write) or 100 ms (erase) The memory mapping the T89C51RD2 software registers in the Extra Flash memory is described in the table below. Table 42. Extra Row Memory Mapping (XAF) Copy of device ID #3 Copy of device ID #2 ...

  • Page 80

    ... Output High Voltage, ports and Output High Voltage, port 0, ALE, PSEN OH1 R RST Pulldown Resistor RST I Logical 0 Input Current ports and Input Leakage Current for P0 only LI Logical Transition Current, ports and 5 T89C51RD2 80 *NOTICE ± 10 MHz ± 10 MHz. (1) Min -0.5 0 0 (6) ( ...

  • Page 81

    ... I Power Supply Current on normal mode CCOP 4243G–8051–05/03 (1) Min = 5 MHz 5 MHz. CC (2) Min -0.5 0 0 (6) ( T89C51RD2 (5) Typ Max Unit Test Conditions MHz µA 120 150 V V 0.7 Freq mA (MHz 0.3 Freq 0.4 Freq mA (MHz (MHz 0.7 Freq ...

  • Page 82

    ... Symbol Parameter Power Supply Current during Flash Write / Erase I CCProgFlash Power Supply Current during EEprom data Write / Erase I CCProgEE I Power Supply Current on idle mode CCIDLE T89C51RD2 82 (2) (5) Min Typ 0.3 Freq 0.4 Freq (MHz) (MHz 0.7 Freq 0.7 Freq (MHz) (MHz ...

  • Page 83

    ... The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 4243G–8051–05/ MHz = 2 3 MHz CC Min -0.5 0 0 (6) ( would be slightly higher if a crystal oscillator used (see Figure RST = V (see Figure 34.). CC SS T89C51RD2 (5) Typ Max Unit Test Conditions ...

  • Page 84

    ... Ports 1, 2 and Maximum total I for all output pins exceeds the test condition than the listed test conditions. T89C51RD2 84 must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater OL Figure 33. I Test Condition, Active Mode ...

  • Page 85

    ... To calculate each AC symbols. take the x value in the correponding column (-M or -L) and use this value in the formula. Example: T for -M and 20 MHz, Standard clock. LLIU 165 ns CCIV T89C51RD2 0.7V CC 0.2V -0 CLCH = 5ns. CHCL Tests in Active and Idle Modes ...

  • Page 86

    ... T T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T89C51RD2 86 Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width ...

  • Page 87

    ... Standard Clock X2 Clock CLCL T T LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T TPLAZ AVLL PXIX A0-A7 INSTR IN T AVIV ADDRESS A8-A15 T89C51RD2 X parameter for - X parameter for - M range L range PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 Units ...

  • Page 88

    ... Table 49. AC Parameters for a Fix Clock Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T RLAZ T WHLH T89C51RD2 88 -M Min Max 130 130 100 0 30 160 165 50 100 75 10 160 Min Max 130 130 100 0 30 160 ...

  • Page 89

    ... Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 4243G–8051–05/03 X parameter for - Standard Clock X2 Clock LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 T89C51RD2 X parameter for - M range L range WHLH T WLWH T T WHQX QVWH DATA OUT Units ...

  • Page 90

    ... Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode Table 51. AC Parameters for a Fix Clock Symbol T XLXL T QVHX T XHQX T XHDX T XHDV T89C51RD2 90 T LLDV T LLWL T AVDV T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 Symbol T XLXL T QVHX T XHQX T ...

  • Page 91

    ... Standard Clock X2 Clock XLXL T XHQX XHDX T XHDV VALID VALID VALID T = 21°C to 27° 0V PROG T89C51RD2 X parameter for - X parameter for - M range L range 133 133 VALID VALID VALID VALID = 5V ± 10%. Min Max CLCL 48 T CLCL 48 T CLCL 48 T CLCL ...

  • Page 92

    ... CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL T /T Cyclic ratio in X2 mode CHCX CLCX External Clock Drive Waveforms V -0.5V CC 0.45V AC Testing Input/Output Waveforms INPUT/OUTPUT T89C51RD2 92 PROGRAMMING ADDRESS DATA GHDX DVGL T T AVGL GHAX T GLGH T EHAZ 0.7V CC 0.2V -0 CLCX ...

  • Page 93

    ... For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ± 20mA. occurs T89C51RD2 - 0.5 for a logic “1” and 0.45V for a logic “0”. CC min for a logic “1” and V max for a logic “0” ...

  • Page 94

    ... WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) T89C51RD2 94 Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. STATE5 STATE6 STATE1 STATE2 THESE SIGNALS ARE NOT ACTIVATED DURING THE ...

  • Page 95

    ... Kbytes T89C51RD2-RLVIL 64 Kbytes T89C51RD2-RLVIM 64 Kbytes T89C51RD2-SLFCL 64 Kbytes T89C51RD2-SLRCM 64 Kbytes T89C51RD2-SLRIM 64 Kbytes T89C51RD2-SLSCL 64 Kbytes T89C51RD2-SLSCM 64 Kbytes T89C51RD2-SLSIL 64 Kbytes T89C51RD2-SLSIM 64 Kbytes T89C51RD2-SLUCM 64 Kbytes T89C51RD2-SLUIM 64 Kbytes T89C51RD2-SMRIL 64 Kbytes 4243G–8051–05/03 Supply Voltage Temperature Range 2.7 - 3.6V Commercial 4.5 - 5.5V Commercial 2.7 - 3.6V Industrial 4 ...

  • Page 96

    ... Part Number Memory Size T89C51RD2-SMSCL 64 Kbytes T89C51RD2-SMSCM 64 Kbytes T89C51RD2-SMSIL 64 Kbytes T89C51RD2-SMSIM 64 Kbytes T89C51RD2-SMUCM 64 Kbytes T89C51RD2-SMUIM 64 Kbytes T89C51RD2 96 Supply Voltage Temperature Range 2.7 - 3.6V Commercial 4.5 - 5.5V Commercial 2.7 - 3.6V Industrial 4.5 - 5.5V Industrial 4.5 - 5.5V Commercial 4.5 - 5.5V Industrial Package Packing ...

  • Page 97

    ... Package Drawings DIL40 4243G–8051–05/03 T89C51RD2 97 ...

  • Page 98

    ... PLCC44 T89C51RD2 98 4243G–8051–05/03 ...

  • Page 99

    ... VQFP44 4243G–8051–05/03 T89C51RD2 99 ...

  • Page 100

    ... VQFP64 T89C51RD2 100 4243G–8051–05/03 ...

  • Page 101

    ... PLCC68 4243G–8051–05/03 T89C51RD2 101 ...

  • Page 102

    ... VQFP64 T89C51RD2 102 4243G–8051–05/03 ...

  • Page 103

    ... Datasheet Change Log for T89C51RD2 Changes from 4243F- 02/01 to 4243G-05/03 4243G–8051–05/03 1. Added bootloader ISP protocol description. T89C51RD2 103 ...

  • Page 104

    ... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...