T89C51RD2-SLSIM Atmel, T89C51RD2-SLSIM Datasheet - Page 10

IC MICRO CTRL 64K FLASH 44PLCC

T89C51RD2-SLSIM

Manufacturer Part Number
T89C51RD2-SLSIM
Description
IC MICRO CTRL 64K FLASH 44PLCC
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of T89C51RD2-SLSIM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Enhanced Features
X2 Feature and Clock
Generation
Description
10
T89C51RD2
In comparison to the original 80C52, the T89C51RD2 implements some new features,
which are
The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called
”X2” provides the following advantages:
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1 shows the clock generation block diagram. X2 bit is
validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
XTAL1
The X2 option
The Dual Data Pointer
The extended RAM
The Programmable Counter Array (PCA)
The Watchdog
The 4 level interrupt priority system
The power-off flag
The ONCE mode
The ALE disabling
Some enhanced features are also located in the UART and the Timer 2
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
F
:
XTAL
2
XTAL1:2
CKCON reg
X2
0
1
F
OSC
CPU control.
State Machine: 6 clock cycles.
4243G–8051–05/03

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