T89C51RD2-SLSIM Atmel, T89C51RD2-SLSIM Datasheet - Page 11

• Manufacturer Part Number: T89C51RD2-SLSIM
• Description: IC MICRO CTRL 64K FLASH 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of T89C51RD2-SLSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Figure 2. Mode Switching Waveforms
4243G–8051–05/03
CPU clock
XTAL1
XTAL1:2
X2 bit
STD Mode
The X2 bit in the CKCON register (Table 4) allows to switch from 12 clock periods per
instruction to 6 clock periods and vice versa. At reset, the standard speed is activated
(STD mode). Setting this bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, SiX2, PcaX2 and WdX2 bits in the CKCON register (Table 4)
allow to switch from standard peripheral speed (12 clock periods per peripheral clock
cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits
are active only in X2 mode.
More information about the X2 mode can be found in the application note ANM072 "How
to take advantage of the X2 features in TS80C51 microcontroller".
Table 4. CKCON Register
CKCON - Clock Control Register (8Fh)
Number
Bit
7
6
5
4
3
7
-
Mnemonic Description
PcaX2
WdX2
T2X2
SiX2
Bit
WdX2
-
6
Reserved
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array clock (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
PcaX2
5
X2 Mode
SiX2
4
T2X2
3
T1X2
2
STD Mode
T89C51RD2
T0X2
1
X2
0
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