T89C51RD2-SLSIM Atmel, T89C51RD2-SLSIM Datasheet - Page 36

• Manufacturer Part Number: T89C51RD2-SLSIM
• Description: IC MICRO CTRL 64K FLASH 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of T89C51RD2-SLSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

36
T89C51RD2
Table 19. SADDR - Slave Address Register (A9h)
Reset Value = 0000 0000b
Not bit addressable
Table 20. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
Number
FE/SM0
Bit
7
6
5
4
3
2
1
0
7
7
Mnemonic
SM0
SM1
SM2
REN
SM1
RB8
TB8
Bit
FE
RI
TI
6
6
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM0 SM1
0
0
1
1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of
the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and
Figure 15. in the other modes.
SM2
5
5
0
1
0
1
Mode Description
0
1
2
3
REN
4
4
Shift Register F
8-bit UART
9-bit UART
9-bit UART
TB8
3
3
Description
Variable
F
Variable
Baud Rate
XTAL
XTAL
/12 (/6 in X2 mode)
/64 or F
RB8
2
2
XTAL
/32 (/32 or 16 in X2 mode)
TI
1
1
4243G–8051–05/03
RI
0
0