ATMEGA8515-16AI Atmel, ATMEGA8515-16AI Datasheet - Page 126

IC AVR MCU 8K 16MHZ IND 44-TQFP

ATMEGA8515-16AI

Manufacturer Part Number
ATMEGA8515-16AI
Description
IC AVR MCU 8K 16MHZ IND 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8515-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8515-16AI
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEGA8515-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Serial Peripheral
Interface – SPI
126
ATmega8515(L)
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega8515 and peripheral devices or between several AVR devices.
The ATmega8515 SPI includes the following features:
Figure 60. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in Figure 61.
The system consists of two Shift Registers, and a Master clock generator. The SPI Mas-
ter initiates the communication cycle when pulling low the Slave Select SS pin of the
desired Slave. Master and Slave prepare the data to be sent in their respective Shift
Registers, and the Master generates the required clock pulses on the SCK line to inter-
change data. Data is always shifted from Master to Slave on the Master Out – Slave In,
MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After
each data packet, the Master will synchronize the Slave by pulling high the Slave Select,
SS, line.
Full Duplex, 3-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
/2/4/8/16/32/64/128
1. Refer to Figure 1 on page 2, and Table 29 on page 67 for SPI pin placement.
DIVIDER
(1)
2512K–AVR–01/10

Related parts for ATMEGA8515-16AI