ATMEGA8535L-8AC Atmel, ATMEGA8535L-8AC Datasheet - Page 111

• Manufacturer Part Number: ATMEGA8535L-8AC
• Description: IC AVR MCU 8K LV 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2502K–AVR–10/06
Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the
fast PWM mode.
Table 46. Compare Output Mode, Fast PWM
Note:
Table 47 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the
phase correct or the phase and frequency correct, PWM mode.
Table 47. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
Note:
• Bit 3 – FOC1A: Force Output Compare for Channel A
• Bit 2 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specify a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to
zero when TCCR1A is written when operating in a PWM mode. When writing a logical
one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform
generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits set-
ting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the
value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
COM1A1/
COM1A1/
COM1B1
COM1B1
0
0
1
1
0
0
1
1
(1)
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is
set. In this case the Compare Match is ignored, but the set or clear is done at TOP.
See “Fast PWM Mode” on page 102 for more details.
set. See “Phase Correct PWM Mode” on page 104. for more details.
COM1A0/
COM1B0
COM1A0/
COM1B0
0
1
0
1
0
1
0
1
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings,
normal port operation, OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match when up-counting. Set
OC1A/OC1B on Compare Match when down-counting.
Set OC1A/OC1B on Compare Match when up-counting. Clear
OC1A/OC1B on Compare Match when down-counting.
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings,
normal port operation OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP
(Non-Inverting)
Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOP
(Inverting)
(1)
ATmega8535(L)
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