ATMEGA8535L-8AC Atmel, ATMEGA8535L-8AC Datasheet - Page 175

• Manufacturer Part Number: ATMEGA8535L-8AC
• Description: IC AVR MCU 8K LV 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Interconnection
Data Transfer and Frame
Format
Transferring Bits
START and STOP Conditions
2502K–AVR–10/06
As depicted in Figure 76, both bus lines are connected to the positive supply voltage
through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or
open-collector. This implements a wired-AND function which is essential to the opera-
tion of the interface. A low level on a TWI bus line is generated when one or more TWI
devices output a zero. A high level is output when all TWI devices tri-state their outputs,
allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to
the TWI bus must be powered in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus
capacitance limit of 400 pF and the 7-bit slave address space. A detailed specification of
the electrical characteristics of the TWI is given in “Two-wire Serial Interface Character-
istics” on page 259. Two different sets of specifications are presented there, one
relevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400 kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line.
The level of the data line must be stable when the clock line is high. The only exception
to this rule is for generating start and stop conditions.
Figure 77. Data Validity
The Master initiates and terminates a data transmission. The transmission is initiated
when the Master issues a START condition on the bus, and it is terminated when the
Master issues a STOP condition. Between a START and a STOP condition, the bus is
considered busy, and no other Master should try to seize control of the bus. A special
case occurs when a new START condition is issued between a START and STOP con-
dition. This is referred to as a REPEATED START condition, and is used when the
Master wishes to initiate a new transfer without relinquishing control of the bus. After a
REPEATED START, the bus is considered busy until the next STOP. This is identical to
the START behavior, and therefore START is used to describe both START and
REPEATED START for the remainder of this datasheet, unless otherwise noted. As
depicted below, START and STOP conditions are signalled by changing the level of the
SDA line when the SCL line is high.
SDA
SCL
Data Stable
Data Change
Data Stable
ATmega8535(L)
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