IC AVR MCU 8K LV 8MHZ COM 44TQFP

ATMEGA8535L-8AC

Manufacturer Part NumberATMEGA8535L-8AC
DescriptionIC AVR MCU 8K LV 8MHZ COM 44TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA8535L-8AC datasheets
 

Specifications of ATMEGA8535L-8AC

Core ProcessorAVRCore Size8-Bit
Speed8MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size8KB (4K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case44-TQFP, 44-VQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
Page 11/22

Download datasheet (257Kb)Embed
PrevNext
Mnemonics
Operands
Description
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
LD
Rd, X
Load Indirect
LD
Rd, X+
Load Indirect and Post-Inc.
LD
Rd, - X
Load Indirect and Pre-Dec.
LD
Rd, Y
Load Indirect
LD
Rd, Y+
Load Indirect and Post-Inc.
LD
Rd, - Y
Load Indirect and Pre-Dec.
LDD
Rd,Y+q
Load Indirect with Displacement
LD
Rd, Z
Load Indirect
LD
Rd, Z+
Load Indirect and Post-Inc.
LD
Rd, -Z
Load Indirect and Pre-Dec.
LDD
Rd, Z+q
Load Indirect with Displacement
LDS
Rd, k
Load Direct from SRAM
ST
X, Rr
Store Indirect
ST
X+, Rr
Store Indirect and Post-Inc.
ST
- X, Rr
Store Indirect and Pre-Dec.
ST
Y, Rr
Store Indirect
ST
Y+, Rr
Store Indirect and Post-Inc.
ST
- Y, Rr
Store Indirect and Pre-Dec.
STD
Y+q,Rr
Store Indirect with Displacement
ST
Z, Rr
Store Indirect
ST
Z+, Rr
Store Indirect and Post-Inc.
ST
-Z, Rr
Store Indirect and Pre-Dec.
STD
Z+q,Rr
Store Indirect with Displacement
STS
k, Rr
Store Direct to SRAM
LPM
Load Program Memory
LPM
Rd, Z
Load Program Memory
LPM
Rd, Z+
Load Program Memory and Post-Inc
SPM
Store Program Memory
IN
Rd, P
In Port
OUT
P, Rr
Out Port
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
CBI
P,b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left Through Carry
ROR
Rd
Rotate Right Through Carry
ASR
Rd
Arithmetic Shift Right
SWAP
Rd
Swap Nibbles
BSET
s
Flag Set
BCLR
s
Flag Clear
BST
Rr, b
Bit Store from Register to T
BLD
Rd, b
Bit load from T to Register
SEC
Set Carry
CLC
Clear Carry
SEN
Set Negative Flag
CLN
Clear Negative Flag
SEZ
Set Zero Flag
CLZ
Clear Zero Flag
SEI
Global Interrupt Enable
CLI
Global Interrupt Disable
SES
Set Signed Test Flag
CLS
Clear Signed Test Flag
SEV
Set Twos Complement Overflow.
CLV
Clear Twos Complement Overflow
SET
Set T in SREG
CLT
Clear T in SREG
SEH
Set Half Carry Flag in SREG
CLH
Clear Half Carry Flag in SREG
MCU CONTROL INSTRUCTIONS
NOP
No Operation
2502KS–AVR–10/06
ATmega8535(L)
Operation
Flags
Rd ← Rr
None
Rd+1:Rd ← Rr+1:Rr
None
Rd ← K
None
Rd ← (X)
None
Rd ← (X), X ← X + 1
None
X ← X - 1, Rd ← (X)
None
Rd ← (Y)
None
Rd ← (Y), Y ← Y + 1
None
Y ← Y - 1, Rd ← (Y)
None
Rd ← (Y + q)
None
Rd ← (Z)
None
Rd ← (Z), Z ← Z+1
None
Z ← Z - 1, Rd ← (Z)
None
Rd ← (Z + q)
None
Rd ← (k)
None
(X) ← Rr
None
(X) ← Rr, X ← X + 1
None
X ← X - 1, (X) ← Rr
None
(Y) ← Rr
None
(Y) ← Rr, Y ← Y + 1
None
Y ← Y - 1, (Y) ← Rr
None
(Y + q) ← Rr
None
(Z) ← Rr
None
(Z) ← Rr, Z ← Z + 1
None
Z ← Z - 1, (Z) ← Rr
None
(Z + q) ← Rr
None
(k) ← Rr
None
R0 ← (Z)
None
Rd ← (Z)
None
Rd ← (Z), Z ← Z+1
None
(Z) ← R1:R0
None
Rd ← P
None
P ← Rr
None
STACK ← Rr
None
Rd ← STACK
None
I/O(P,b) ← 1
None
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
SREG(s) ← 1
SREG(s)
SREG(s) ← 0
SREG(s)
T ← Rr(b)
T
Rd(b) ← T
None
C ← 1
C
C ← 0
C
N ← 1
N
N ← 0
N
Z ← 1
Z
Z ← 0
Z
I ← 1
I
I ← 0
I
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
V
T ← 1
T
T ← 0
T
H ← 1
H
H ← 0
H
None
#Clocks
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
11