ATMEGA162L-8AC Atmel, ATMEGA162L-8AC Datasheet
ATMEGA162L-8AC
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ATMEGA162L-8AC Summary of contents
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... ATmega162V – 2.4 - 4.0V for ATmega162U – 2.7 - 5.5V for ATmega162L – 4.5 - 5.5V for ATmega162 • Speed Grades – MHz for ATmega162V – MHz for ATmega162L/U – MHz for ATmega162 ® 8-bit Microcontroller 8-bit ATmega162 ATmega162V ...
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Pin Configurations Disclaimer ATmega162(V/U/L) 2 Figure 1. Pinout ATmega162 (OC0/T0) PB0 (OC2/T1) PB1 (RXD1/AIN0) PB2 (TXD1/AIN1) PB3 (SS/OC3B) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 (TXD0) PD1 (INT0/XCK1) PD2 (INT1/ICP3) PD3 (TOSC1/XCK0/OC3A) PD4 (OC1A/TOSC2) PD5 (WR) PD6 ...
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Overview Block Diagram 2513C–AVR–09/02 The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the sys- ...
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... Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications ...
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ATmega161 Compatibility Mode Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) 2513C–AVR–09/02 Programming the M161C will change the following functionality: • The extended I/O map will be configured as internal RAM once the M161C Fuse ...
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Port D (PD7..PD0) Port E(PE2..PE0) RESET XTAL1 XTAL2 About Code Examples ATmega162(V/U/L) 6 Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both ...
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AVR CPU Core Introduction Architectural Overview 2513C–AVR–09/02 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, ...
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ALU – Arithmetic Logic Unit Status Register ATmega162(V/U/L) 8 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can ...
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The AVR Status Register – SREG – is defined as: Bit Read/Write R/W R/W R/W Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit ...
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General Purpose Register File ATmega162(V/U/L) 10 The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit ...
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The X-register, Y-register, and Z-register Stack Pointer 2513C–AVR–09/02 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, ...
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Instruction Execution Timing Reset and Interrupt Handling ATmega162(V/U/L) 12 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. ...
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Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-programming” on page 214. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all ...
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Interrupt Response Time ATmega162(V/U/L) 14 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set global interrupt enable sleep ; ...
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AVR ATmega162 Memories In-System Reprogrammable Flash Program Memory 2513C–AVR–09/02 This section describes the different memories in the ATmega162. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega162 features an ...
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SRAM Data Memory ATmega162(V/U/L) 16 Figure 9 shows how the ATmega162 SRAM Memory is organized. Memory configura- tion B refers to the ATmega161 compatibility mode, configuration A to the non- compatible mode. The ATmega162 is a complex microcontroller with more ...
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Data Memory Access Times 2513C–AVR–09/02 When using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 (+160) I/O Registers, and the ...
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EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register – EEARH and EEARL ATmega162(V/U/L) 18 The ATmega162 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be ...
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The EEPROM Data Register – EEDR The EEPROM Control Register – EECR 2513C–AVR–09/02 Bit MSB Read/Write R/W R/W R/W Initial Value • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the ...
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ATmega162(V/U/L) 20 can be omitted. See “Boot Loader Support – Read-While-Write Self-programming” on page 214 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write ...
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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter- rupts globally) so that no interrupts will occur during execution of these ...
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Preventing EEPROM Corruption ATmega162(V/U/L) 22 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ...
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I/O Memory 2513C–AVR–09/02 The I/O space definition of the ATmega162 is shown in “Register Summary” on page 272. All ATmega162 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD ...
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External Memory Interface Overview Using the External Memory Interface ATmega162(V/U/L) 24 With all the features the External Memory Interface provides well suited to operate as an interface to memory devices such as external SRAM and FLASH, and peripherals ...
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Address Latch Requirements 2513C–AVR–09/02 The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special Function IO Register – SFIOR. When the ...
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Pull-up and Bus Keeper Timing ATmega162(V/U/L) 26 The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port reg- ister is written to one. To reduce power consumption in sleep mode recommended to disable the ...
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Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 T1 System Clock (CLK ) CPU ALE A15:8 Prev. addr. DA7:0 Prev. data WR DA7:0 (XMBK = 0) Prev. data DA7:0 (XMBK = 1) RD ...
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XMEM Register Description MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR ATmega162(V/U/L) 28 Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = System Clock (CLK ) CPU ALE A15:8 Prev. ...
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Table 2. Sector Limits with Different Settings of SRL2..0 SRL2 SRL1 SRL0 • Bit 1 ...
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Special Function IO Register – SFIOR Using all Locations of External Memory Smaller than 64 KB ATmega162(V/U/L) 30 Bit TSM XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 6 – XMBK: External ...
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Figure 17. Address Map with 32 KB External Memory Memory Configuration A AVR Memory Map 0x0000 Internal Memory 0x04FF 0x0500 External 0x7FFF 0x8000 Memory 0x84FF 0x8500 (Unused) 0xFFFF 2513C–AVR–09/02 When the device is set in ATmega161 compatibility mode, the internal ...
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Using all 64KB Locations of External Memory ATmega162(V/U/L) 32 Since the external memory is mapped after the internal memory as shown in Figure 11, only 64,256 Bytes of external memory are available by default (address space 0x0000 to 0x05FF is ...
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System Clock and Clock Options Clock Systems and their Distribution CPU clock – clk CPU I/O clock – clk I/O Flash clock – clk FLASH Asynchronous Timer clock – clk ASY 2513C–AVR–09/02 Figure 18 presents the principal clock systems in ...
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Clock Sources Default Clock Source Crystal Oscillator ATmega162(V/U/L) 34 The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed ...
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Figure 19. Crystal Oscillator Connections C2 C1 The Oscillator can operate in four different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3:1 as shown in Table 7. Table 7. ...
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Low-frequency Crystal Oscillator ATmega162(V/U/L) 36 Table 8. Start-up Times for the Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and CKSEL0 SUT1:0 Power-save 1 01 16K 16K 16K CK Notes: 1. These options ...
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Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL 2513C–AVR–09/02 The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is nominal value at 3V and 8.0 MHz frequency exceed the specification of the ...
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External Clock ATmega162(V/U/L) 38 Table 13. Internal RC Oscillator Frequency Range. Min Frequency in Percentage of OSCCAL Value Nominal Frequency 0x00 50% 0x3F 75% 0x7F 100% 0x80 - 0xFF To drive the device from an external clock source, XTAL1 should ...
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Clock output buffer Timer/Counter Oscillator System Clock Prescaler Clock Prescale Register – CLKPR 2513C–AVR–09/02 When the CKOUT Fuse is programmed, the system clock will be output on PortB 0. This mode is suitable when chip clock is used to drive ...
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ATmega162(V/U/L) 40 The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro- grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0100”, giving a division factor ...
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Power Management and Sleep Modes MCU Control Register – MCUCR MCU Control and Status Register – MCUCSR 2513C–AVR–09/02 Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes ...
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Extended MCU Control Register – EMCUCR Idle Mode Power-down Mode ATmega162(V/U/L) 42 Bit SM0 SRL2 SRL1 Read/Write R/W R/W R/W Initial Value • Bit 7 – SM0: Sleep Mode Select Bit 0 The Sleep ...
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Power-save Mode Standby Mode Extended Standby Mode Table 17. Active Clock domains and Wake up sources in the different sleep modes Active Clock domains Sleep Mode clk clk CPU FLASH Idle Power-down Power-save (1) Standby (1) Extended Standby Notes: 1. ...
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Minimizing Power Consumption Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins On-chip Debug System ATmega162(V/U/L) 44 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep ...
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System Control and Reset Resetting the AVR Reset Sources 2513C–AVR–09/02 During Reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must be ...
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Power-on Reset ATmega162(V/U/L) 46 Figure 21. Reset Logic V CC BODLEVEL [ 2..0] Pull-up Resistor SPIKE RESET FILTER JTAG Reset Register CKSEL[3:0] Table 18. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold Voltage (1) ...
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External Reset 2513C–AVR–09/02 Figure 22. MCU Start-up, RESET Tied POT RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 23. MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET An External ...
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... This guarantees that a Brown-out Reset will occour before voltage where correct operation of the microcontroller is no longer guarateed. This test is performed using BODLEVEL = 110 for ATmega162V, BODLEVEL = 101 for ATmega162L, and BODLEVEL = 100 for ATmega162. 2. BODLEVEL = 011 for ATmega162U. Otherwise reserved. Table 20. Brown-out Hysteresis ...
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Watchdog Reset MCU Control and Status Register – MCUCSR 2513C–AVR–09/02 Figure 25. Brown-out Reset During Operation BOT- RESET TIME-OUT INTERNAL RESET When the Watchdog times out, it will generate a short reset pulse of one CK cycle ...
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Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer ATmega162(V/U/L) 50 • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or ...
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Watchdog Timer Control Register – WDTCR 2513C–AVR–09/02 shown in Table 22. Safety level 0 corresponds to the setting in ATmega161. There is no restriction on enabling the WDT in any of the safety levels. Refer to “Timed Sequences for Changing ...
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ATmega162(V/U/ the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow- ing procedure must be followed the same operation, write a logic one to WDCE and WDE. A logic one must ...
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The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. ...
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Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 ATmega162(V/U/L) 54 The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level. ...
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Interrupts Interrupt Vectors in ATmega162 2513C–AVR–09/02 This section describes the specifics of the interrupt handling as performed in ATmega162. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 24 shows ...
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ATmega162(V/U/L) 56 Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-programming” on page 214. 2. When the IVSEL bit in GICR is set, ...
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Table 26 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at ...
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ATmega162(V/U/L) 58 0x03A ldi r16,low(RAMEND) 0x03B out SPL,r16 0x03C sei 0x03D <instr> ... ... ... When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before ...
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Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR 2513C–AVR–09/02 When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any ...
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ATmega162(V/U/L) 60 IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to Boot Flash ...
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I/O-Ports Introduction 2513C–AVR–09/02 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with ...
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Ports as General Digital I/O Configuring the Pin ATmega162(V/U/L) 62 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 29. General Digital I/O ...
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Reading the Pin Value 2513C–AVR–09/02 enabled state is fully acceptable high-impedant environment will not notice the dif- ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR ...
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ATmega162(V/U/L) 64 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region ...
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Digital Input Enable and Sleep Modes 2513C–AVR–09/02 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned ...
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Unconnected pins Alternate Port Functions ATmega162(V/U/ some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described ...
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Table 28 summarizes the function of the overriding signals. The pin and port indexes from Figure 32 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table ...
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Special Function IO Register – SFIOR Alternate Functions of Port A ATmega162(V/U/L) 68 Bit TSM XMBK XMM2 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is ...
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Table 30. Overriding Signals for Alternate Functions in PA7..PA4 Signal PA7/AD7/ Name PCINT7 PA6/AD6/PCINT6 PUOE SRE SRE (1) PUOV ~(WR + ADA ) • ~(WR + ADA) • PORTA7 PORTA6 DDOE SRE SRE DDOV WR + ADA WR + ...
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Alternate Functions Of Port B ATmega162(V/U/L) 70 The Port B pins with alternate functions are shown in Table 32. Table 32. Port B Pins Alternate Functions Port Pin Alternate Functions PB7 SCK (SPI Bus Serial Clock) PB6 MISO (SPI Bus ...
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OC3B, Output Compare Match B output: The PB4 pin can serve as an external output for the Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC3B ...
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ATmega162(V/U/L) 72 Table 33. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/SCK PB6/MISO PUOE SPE • MSTR SPE • MSTR PUOV PORTB7 • PORTB6 • PUD PUD DDOE SPE • MSTR SPE • MSTR DDOV 0 0 PVOE ...
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Alternate Functions of Port C 2513C–AVR–09/02 The Port C pins with alternate functions are shown in Table 35. If the JTAG interface is enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be acti- vated even if a ...
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ATmega162(V/U/L) 74 • A13/TMS/PCINT13 – Port C, Bit 5 A13, External memory interface address bit 13. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin ...
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Table 36. Overriding Signals for Alternate Functions in PC7..PC4 PC7/A15/TDI Signal Name /PCINT15 PUOE (XMM < 1) • SRE + JTAGEN PUOV JTAGEN DDOE SRE • (XMM<1) + JTAGEN DDOV JTAGEN PVOE SRE • (XMM<1) PVOV A15 (1) DIEOE ...
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Alternate Functions of Port D ATmega162(V/U/L) 76 The Port D pins with alternate functions are shown in Table 38. Table 38. Port D Pins Alternate Functions Port Pin Alternate Function PD7 RD (Read strobe to external memory) PD6 WR (Write ...
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TOSC1/XCK0/OC3A – Port D, Bit 4 TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asyn- chronous clocking of Timer/Counter2, pin PD4 is disconnected from the port, and becomes the input ...
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ATmega162(V/U/L) 78 • RXD0 – Port D, Bit 0 RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When USART0 forces this ...
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Alternate Functions of Port E 2513C–AVR–09/02 The Port E pins with alternate functions are shown in Table 41. Table 41. Port E Pins Alternate Functions Port Pin Alternate Function PE2 OC1B (Timer/Counter1 Output CompareB Match Output) PE1 ALE (Address Latch ...
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Register Description for I/O-Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input ...
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Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE ...
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External Interrupts MCU Control Register – MCUCR ATmega162(V/U/L) 82 The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2..0 or PCINT15..0 ...
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Extended MCU Control Register – EMCUCR 2513C–AVR–09/02 Table 43. Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request Any logical change on INT1 generates an interrupt request ...
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General Interrupt Control Register – GICR ATmega162(V/U/L) 84 Bit INT1 INT0 INT2 Read/Write R/W R/W R/W Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set ...
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General Interrupt Flag Register – GIFR 2513C–AVR–09/02 Bit INTF1 INTF0 INTF2 Read/Write R/W R/W R/W Initial Value • Bit 7 – INTF1: External Interrupt Flag 1 When an edge or logic change on the ...
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Pin Change Mask Register 1 – PCMSK1 Pin Change Mask Register 0 – PCMSK0 ATmega162(V/U/L) 86 Bit PCINT15 PCINT14 PCINT13 Read/Write R/W R/W R/W Initial Value • Bit 7..0 – PCINT15..8: Pin Change Enable ...
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Timer/Counter0 with PWM Overview Registers 2513C–AVR–09/02 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator ...
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Definitions Timer/Counter Clock Sources ATmega162(V/U/L) 88 inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk T The double buffered Output Compare Register (OCR0) is compared with the ...
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Counter Unit Output Compare Unit 2513C–AVR–09/02 The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 34 shows a block diagram of the counter and its surroundings. Figure 34. Counter Unit Block Diagram DATA BUS count ...
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Force Output Compare Compare Match Blocking by TCNT0 Write ATmega162(V/U/L) 90 Figure 35 shows a block diagram of the output compare unit. Figure 35. Output Compare Unit, Block Diagram OCRn top bottom Waveform Generator FOCn WGMn1:0 The OCR0 Register is ...
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Using the Output Compare Unit Compare Match Output Unit 2513C–AVR–09/02 Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the output compare ...
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Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega162(V/U/L) 92 The design of the output compare pin logic allows initialization of the OC0 state before the output is enabled. Note ...
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Fast PWM Mode 2513C–AVR–09/02 Figure 37. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period 1 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 flag. If the interrupt is enabled, the ...
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ATmega162(V/U/L) 94 non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. Figure 38. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow ...
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Phase Correct PWM Mode 2513C–AVR–09/02 The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from ...
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Timer/Counter Timing Diagrams ATmega162(V/U/L) 96 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f The N variable represents the prescale factor (1, 8, ...
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Figure 42. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 43 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ...
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Timer/Counter Register Description Timer/Counter Control Register – TCCR0 ATmega162(V/U/L) 98 Bit FOC0 WGM00 COM01 Read/Write W R/W R/W Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only ...
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When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 48 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a Normal or CTC mode (non-PWM). ...
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Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK ATmega162(V/U/L) 100 • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table ...
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Timer/Counter Interrupt Flag Register – TIFR 2513C–AVR–09/02 • Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match ...
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Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega162(V/U/L) 102 Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler mod- ule, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counter3, Timer/Counter1, ...
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Special Function IO Register – SFIOR 2513C–AVR–09/02 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system ...
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Timer/Counter (Timer/Counter1 and Timer/Counter3) Restriction in ATmega161 Compatibility Mode Overview ATmega162(V/U/L) 104 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., ...
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Registers 2513C–AVR–09/02 Figure 46. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 32 on page 70, and Table 38 on page 76 for ...
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Definitions Compatibility ATmega162(V/U/L) 106 (OCnA/B). See “Output Compare Units” on page 113. The compare match event will also set the Compare Match Flag (OCFnA/B) which can be used to generate an output compare interrupt request. The Input Capture Register can ...
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Accessing 16-bit Registers 2513C–AVR–09/02 The TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...
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ATmega162(V/U/L) 108 Therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. The following code examples show how atomic read of ...
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Reusing the Temporary High Byte Register 2513C–AVR–09/02 The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B or ICRn Registers can be done by using the same principle. (1) ...
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Timer/Counter Clock Sources Counter Unit ATmega162(V/U/L) 110 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located ...
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Input Capture Unit 2513C–AVR–09/02 how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 116. The Timer/Counter Overflow Flag (TOVn) is set according ...
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Input Capture Trigger Source Noise Canceler Using the Input Capture Unit ATmega162(V/U/L) 112 Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the ...
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Output Compare Units 2513C–AVR–09/02 (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt handler is used). The 16-bit ...
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Force Output Compare Compare Match Blocking by TCNTn Write Using the Output Compare Unit ATmega162(V/U/L) 114 sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but ...
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Compare Match Output Unit 2513C–AVR–09/02 The Compare Output mode (COMnx1:0) bits have two functions. The waveform genera- tor uses the COMnx1:0 bits for defining the output compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the ...
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Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega162(V/U/L) 116 The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 ...
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Figure 51. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 1 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used ...
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Fast PWM Mode ATmega162(V/U/L) 118 The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) pro- vides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope ...
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OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program ...
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Phase Correct PWM Mode ATmega162(V/U/L) 120 The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode ...
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Phase and Frequency Correct PWM Mode 2513C–AVR–09/02 ICFn flag is set accordingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to gener- ate ...
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ATmega162(V/U/L) 122 pared to the single-slope operation. However, due to the symmetric feature of the dual- slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct ...
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TCNTn and the OCRnx. As Figure 54 shows the output generated is, in contrast to the phase correct mode, sym- metrical in all periods. Since ...
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Timer/Counter Timing Diagrams ATmega162(V/U/L) 124 The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCRnx ...
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Figure 57. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old ...
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Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter3 Control Register A – TCCR3A ATmega162(V/U/L) 126 Bit COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value Bit COM3A1 COM3A0 ...
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Table 54 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 54. Compare Output Mode, Fast PWM COMnA1/ COMnA0/ COMnB1 COMnB0 Description 0 0 Normal port operation, OCnA/OCnB disconnected ...
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Table 56. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...
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Timer/Counter1 Control Register B – TCCR1B Timer/Counter3 Control Register B – TCCR3B 2513C–AVR–09/02 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value Bit ICNC3 ICES3 – Read/Write R/W R/W R ...
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ATmega162(V/U/L) 130 • Bit 2:0 – CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 55 and Figure 56. Table 57. Clock Select Bit Description Timer/Counter1 CS12 CS11 CS10 ...
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Timer/Counter1 – TCNT1H and TCNT1L Timer/Counter3 – TCNT3H and TCNT3L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Output Compare Register 3 A – OCR3AH and OCR3AL Output Compare Register ...
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Input Capture Register 1 – ICR1H and ICR1L Input Capture Register 3 – ICR3H and ICR3L Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega162(V/U/L) 132 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter ...
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Extended Timer/Counter Interrupt Mask Register – (1) ETIMSK 2513C–AVR–09/02 • Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo- bally ...
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Timer/Counter Interrupt Flag (1) Register – TIFR ATmega162(V/U/L) 134 Bit TOV1 OCF1A OC1FB Read/Write R/W R/W R/W Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are ...
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Extended Timer/Counter Interrupt Flag Register – (1) ETIFR 2513C–AVR–09/02 Bit ICF3 Read/Write R R R/W Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer3 bits are described in ...
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Timer/Counter2 with PWM and Asynchronous operation Overview Registers ATmega162(V/U/L) 136 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase ...
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Definitions Timer/Counter Clock Sources 2513C–AVR–09/02 The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock ...
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Counter Unit Output Compare Unit ATmega162(V/U/L) 138 The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 60 shows a block diagram of the counter and its surrounding environment. Figure 60. Counter Unit Block Diagram DATA ...
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Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit 2513C–AVR–09/02 Figure 61. Output Compare Unit, Block Diagram OCRn top bottom Waveform Generator FOCn WGMn1:0 The OCR2 Register is double buffered when using any of the ...
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Compare Match Output Unit ATmega162(V/U/L) 140 resulting in incorrect Waveform Generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The Setup of the OC2 should be performed before setting the Data Direction Register ...
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Compare Output Mode and Waveform Generation Modes of Operation Normal Mode 2513C–AVR–09/02 The design of the Output Compare pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for ...
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Clear Timer on Compare Match (CTC) Mode ATmega162(V/U/L) 142 In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when ...
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Fast PWM Mode 2513C–AVR–09/02 The fast Pulse Width Modulation or fast PWM mode (WGM21 provides a high fre- quency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter ...
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Phase Correct PWM Mode ATmega162(V/U/L) 144 The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 ...
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Timer/Counter Timing Diagrams 2513C–AVR–09/02 The Timer/Counter Overflow Flag ( TOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM ...
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ATmega162(V/U/L) 146 Figure 67. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 68 shows the setting of OCF2 in all modes except CTC mode. Figure 68. Timer/Counter Timing Diagram, ...
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Timer/Counter Register Description Timer/Counter Control Register – TCCR2 2513C–AVR–09/02 Bit FOC2 WGM20 COM21 Read/Write W R/W R/W Initial Value • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active ...
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ATmega162(V/U/L) 148 • Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the ...
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Timer/Counter Register – TCNT2 Output Compare Register – OCR2 2513C–AVR–09/02 • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 64. Table 64. Clock Select Bit ...
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Asynchronous operation of the Timer/Counter Asynchronous Status Register – ASSR ATmega162(V/U/L) 150 Bit – – – Read/Write Initial Value • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to ...
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Asynchronous Operation of Timer/Counter2 2513C–AVR–09/02 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching ...
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Timer/Counter Interrupt Mask Register – TIMSK ATmega162(V/U/L) 152 no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or Extended Standby mode when the Timer ...
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Timer/Counter Interrupt Flag Register – TIFR 2513C–AVR–09/02 Bit TOV1 OCF1A OC1FB Read/Write R/W R/W R/W Initial Value • Bit 4 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a ...
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Timer/Counter Prescaler Special Function IO Register – SFIOR ATmega162(V/U/L) 154 Figure 70. Prescaler for Timer/Counter2 clk clk I/O T2S Clear TOSC1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 is named clk the main system I/O clock clk ...
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Serial Peripheral Interface – SPI 2513C–AVR–09/02 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega162 and peripheral devices or between several AVR devices. The ATmega162 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer ...
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ATmega162(V/U/L) 156 When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data ...
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The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, ...
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ATmega162(V/U/L) 158 The following code examples show how to initialize the SPI as a slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; ...
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SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR 2513C–AVR–09/02 When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO ...
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ATmega162(V/U/L) 160 • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR ...
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SPI Status Register – SPSR SPI Data Register – SPDR 2513C–AVR–09/02 Bit SPIF WCOL – Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is ...
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Data Modes ATmega162(V/U/L) 162 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 73 and Figure 74. ...
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USART Dual USART 2513C–AVR–09/02 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation ...
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ATmega162(V/U/L) 164 Figure 75. USART Block Diagram UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: 1. Refer to Figure 1 on page 2, Table 34 on page 72, Table 39 on page ...
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AVR USART vs. AVR UART – Compatibility Clock Generation 2513C–AVR–09/02 The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver ...
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Internal Clock Generation – The Baud Rate Generator ATmega162(V/U/L) 166 Signal description: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK ...
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Double Speed Operation (U2X) External Clock Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock 2513C–AVR–09/02 The transfer rate can be doubled by setting the U2X bit in UCSRA. ...
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Frame Formats Parity Bit Calculation ATmega162(V/U/L) 168 A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations ...
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USART Initialization 2513C–AVR–09/02 If used, the parity bit is located between the last data bit and first stop bit of a serial frame. The USART has to be initialized before any communication can take place. The initial- ization process normally ...
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Data Transmission – The USART Transmitter Sending Frames with Data Bit ATmega162(V/U/L) 170 baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined ...
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Sending Frames with 9 Data Bit Transmitter Flags and Interrupts 2513C–AVR–09/02 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written ...
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Parity Generator Disabling the Transmitter Data Reception – The USART Receiver ATmega162(V/U/L) 172 Empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) flag bit is set one when the entire frame in ...
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Receiving Frames with Data Bits 2513C–AVR–09/02 The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted ...
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Receiving Frames with 9 Data Bits ATmega162(V/U/L) 174 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, ...
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Receive Compete Flag and Interrupt Receiver Error Flags 2513C–AVR–09/02 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will ...
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Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery ATmega162(V/U/L) 176 The Parity Checker is active when the high USART Parity Mode (UPM1) bit is set. Type of parity check to be performed (odd ...
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Asynchronous Data Recovery 2513C–AVR–09/02 (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 79. Start Bit Sampling RxD IDLE Sample (U2X = ...
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Asynchronous Operational Range ATmega162(V/U/L) 178 Figure 81. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = Sample (U2X = 1) The same majority voting is done to the ...
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Multi-processor Communication Mode 2513C–AVR–09/02 Table 71. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit) R (%) R slow 5 93.20 6 94.12 7 94.81 8 95.36 9 95.81 10 96.17 Table ...
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Using MPCM ATmega162(V/U/L) 180 The Multi-processor Communication mode enables several slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed particular slave ...
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Accessing UBRRH/ UCSRC Registers Write Access 2513C–AVR–09/02 The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. When doing a write access of this I/O location, ...
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Read Access ATmega162(V/U/L) 182 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any of these registers. The read access is controlled ...
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USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA 2513C–AVR–09/02 Bit Read/Write R/W R/W R/W Initial Value The USART Transmit Data Buffer Register and USART Receive ...
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USART Control and Status Register B – UCSRB ATmega162(V/U/L) 184 UDRE is set after a Reset to indicate that the transmitter is ready. • Bit 4 – FE: Frame Error This bit is set if the next character in the ...
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Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty inter- rupt will be generated only if the UDRIE bit is written to ...
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USART Control and Status (1) Register C – UCSRC ATmega162(V/U/L) 186 Bit URSEL UMSEL UPM1 Read/Write R/W R/W R/W Initial Value Note: 1. The UCSRC Register shares the same I/O location as the UBRRH ...
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USART Baud Rate Registers – (1) UBRRL and UBRRH 2513C–AVR–09/02 • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size frame the receiver ...
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Examples of Baud Rate Setting Table 78. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 ...
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Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k 15 ...
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Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 ...
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Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k 68 ...
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Analog Comparator Analog Comparator Control and Status Register – ACSR ATmega162(V/U/L) 192 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than ...
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ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut- ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. • Bit ...
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... JTAG Interface” on page 247 and “IEEE 1149.1 (JTAG) Boundary-scan” on page 201, respectively. The On-chip Debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Figure 83 shows a block diagram of the JTAG interface and the On-chip Debug system. ...
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Figure 83. Block Diagram DEVICE BOUNDARY TDI TDO TAP TCK CONTROLLER TMS INSTRUCTION REGISTER ID REGISTER M BYPASS U REGISTER X BREAKPOINT SCAN CHAIN ADDRESS DECODER 2513C–AVR–09/02 The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ...
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ATmega162(V/U/L) 196 Figure 84. TAP Controller State Diagram 1 Test-Logic-Reset Run-Test/Idle Select-DR Scan Select-IR Scan 0 1 Capture-DR 0 Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- ...
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TAP Controller Using the Boundary- scan Chain 2513C–AVR–09/02 The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 84 depend ...
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... The AVR Studio enables the user to fully control execution of programs on an AVR device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. AVR Studio supports source level execution of Assembly pro- grams assembled with Atmel Corporation’s AVR Assembler and C programs compiled with third party vendors’ compilers. ® ...
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... Capabilities 2513C–AVR–09/02 The On-chip debug support is considered being private JTAG instructions, and distrib- uted within ATMEL and to selected 3rd party vendors only. Instruction opcodes are listed for reference. Private JTAG instruction for accessing On-chip debug system. Private JTAG instruction for accessing On-chip debug system. ...
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Bibliography ATmega162(V/U/L) 200 For more information about general Boundary-scan, the following literature can be consulted: • IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993 • Colin Maunder: The Board Designers Guide to Testable Logic ...