IC 8051 MCU FLASH 64K 40DIP

AT89C51ED2-3CSIM

Manufacturer Part NumberAT89C51ED2-3CSIM
DescriptionIC 8051 MCU FLASH 64K 40DIP
ManufacturerAtmel
Series89C
AT89C51ED2-3CSIM datasheet
 

Specifications of AT89C51ED2-3CSIM

Core Processor8051Core Size8-Bit
Speed60MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o34
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Eeprom Size2K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeExternal
Operating Temperature-40°C ~ 85°CPackage / Case40-DIP (0.600", 15.24mm)
Data Bus Width8 bitData Ram Size64 KB
Interface TypeSPI, UARTMaximum Clock Frequency60 MHz
Number Of Programmable I/os32Number Of Timers3 x 16 bit
Operating Supply Voltage2.7 V to 5.5 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantData Converters-
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Features
80C52 Compatible
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
ISP (In-System Programming) Using Standard V
2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Loader
High-speed Architecture
– In Standard Mode:
• 40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
• 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
• 20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
• 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
64K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100k Write Cycles
On-chip 1792 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)
– 768 Bytes Selected at Reset for T89C51RD2 Compatibility
On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
100K Write Cycles
Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independent Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
16-bit Programmable Counter Array
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag
Power Control Modes: Idle Mode, Power-down Mode
Single Range Power Supply: 2.7V to 5.5V
Industrial Temperature Range (-40 to +85°C)
Packages: PLCC44, VQFP44, PLCC68, VQFP64
Power Supply
CC
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2

AT89C51ED2-3CSIM Summary of contents

  • Page 1

    ... On-chip 1792 bytes Expanded RAM (XRAM) – Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes) – 768 Bytes Selected at Reset for T89C51RD2 Compatibility • On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only) • 100K Write Cycles • Dual Data Pointer • ...

  • Page 2

    ... V The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of internal RAM, a 9-source 4-level interrupt controller and three timer/counters. The AT89C51ED2 pro- vides 2048 bytes of EEPROM for nonvolatile data storage. In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of 1792 ...

  • Page 3

    ... Parallel I/O Ports & Timer 0 INT External Bus Timer 1 Ctrl Port 0 Port 1 Port 2 Port 3 (2) (2) (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 AT89C51RD2/ED2 (1) (1) (1) (1) (1) EEPROM* Watch PCA Timer2 Keyboard -dog (AT89C51ED2) BOOT Regulator SPI POR / PFD ROM Port4 Port 5 (1) (1)(1)( ...

  • Page 4

    SFR Mapping The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, ...

  • Page 5

    Table 3-3. Interrupt SFRs Mnemonic Add Name IEN0 A8h Interrupt Enable Control 0 IEN1 B1h Interrupt Enable Control 1 IPH0 B7h Interrupt Priority Control High 0 IPL0 B8h Interrupt Priority Control Low 0 IPH1 B3h Interrupt Priority Control High 1 ...

  • Page 6

    Table 3-5. Timer SFRs Mnemonic Add Name TL2 CCh Timer/Counter 2 Low Byte Table 3-6. PCA SFRs Mnemo -nic Add Name CCON D8h PCA Timer/Counter Control CMOD D9h PCA Timer/Counter Mode CL E9h PCA Timer/Counter Low Byte CH F9h PCA ...

  • Page 7

    ... Add Name KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register Table 3-10. EEPROM data Memory SFR (AT89C51ED2 only) Mnemonic Add Name EECON D2h EEPROM Data Control Table 3-11. SFR Mapping Bit Addressable 0/8 1/9 ...

  • Page 8

    Table 3-11. SFR Mapping P2 A0h 1111 1111 SCON SBUF 98h 0000 0000 XXXX XXXX P1 90h 1111 1111 TCON TMOD 88h 0000 0000 0000 0000 P0 SP 80h 0000 0111 1111 1111 0/8 1/9 AT89C51RD2/ED2 8 AUXR1 0XXX X0X0 ...

  • Page 9

    Pin Configurations Figure 4-1. Pin Configurations P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEx4/MOSI P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI 4235K–8051–05/ RST 10 P3.0/RxD 11 AT89C51RD2/ED2 12 NIC* PLCC44 P3.1/TxD 13 P3.2/INT0 14 ...

  • Page 10

    ... P4.7 45 P2.2/A10 44 P2.1/A9 43 P2.0/A8 42 P4.6 41 NIC 40 VSS VQFP64 39 P4.5 38 XTAL1 37 XTAL2 36 P3. P4.4 34 P3. P4.3 60 P5.0 59 P2.4/A12 58 P2.3/A11 57 P4.7 56 P2.2/A10 55 P2.1/A9 54 P2.0/A8 AT89C51ED2 53 P4.6 PLCC68 52 NIC 51 VSS 50 P4.5 49 XTAL1 48 XTAL2 47 P3. P4.4 45 P3. P4.3 NIC: Not Internaly Connected 4235K–8051–05/08 ...

  • Page 11

    Table 4-1. Pin Description Pin Number Mnemonic PLCC44 VQFP44 P0 P1 ...

  • Page 12

    Table 4-1. Pin Description (Continued) Pin Number Mnemonic PLCC44 VQFP44 9 3 XTALA1 21 15 XTALA2 20 14 P2 P3.0 - P3.7 11 ...

  • Page 13

    Table 4-1. Pin Description (Continued) Pin Number Mnemonic PLCC44 VQFP44 ALE/PRO PSEN 4235K–8051–05/08 Type PLCC68 VQFP64 Name and Function Address Latch Enable/Program Pulse: Output pulse for latching the (I) ...

  • Page 14

    Port Types AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the ...

  • Page 15

    Oscillator To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals. 6.1 Registers Table 6-1. CKRL – Clock Reload Register (97h) ...

  • Page 16

    Functional Block Diagram Figure 6-1. Functional Oscillator Block Diagram Reset F Xtal1 OSC Osc Xtal2 :2 6.2.1 Prescaler Divider • A hardware RESET puts the prescaler divider in the following state: • CKRL = FFh: F • Any value ...

  • Page 17

    Enhanced Features In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new features, which are • X2 option • Dual Data Pointer • Extended RAM • Programmable Counter Array (PCA) • Hardware Watchdog • SPI interface • 4-level ...

  • Page 18

    Figure 7-1. Figure 7-2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 Bit CPU Clock STD Mode The X2 bit in the CKCON0 register (see Table 7-1) allows a switch from 12 clock periods per instruction to 6 clock periods and vice ...

  • Page 19

    Bit Number Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”) Not bit addressable Table 7-2. CKCON1 - Clock Control Register (AFh Bit Number 4235K–8051–05/08 Bit ...

  • Page 20

    Bit Number Reset Value = XXXX XXX0b Not bit addressable AT89C51RD2/ED2 20 Bit Mnemonic Description - Reserved - Reserved SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this ...

  • Page 21

    Dual Data Pointer Register (DPTR) The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external ...

  • Page 22

    Reset Value = XXXX XX0X0b Not bit addressable Note: ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: ; unless an extra INC AUXR1 is added ; 00A2 ; 0000 909000MOV ...

  • Page 23

    Expanded RAM (XRAM) The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM) space for increased data parameter handling and high level language usage. AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up to 1792 bytes (see The ...

  • Page 24

    XRAM as explained in Table 9-1. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX ...

  • Page 25

    Bit Number 1 0 Reset Value = 0X00 1000 Not bit addressable 4235K–8051–05/08 Bit Mnemonic Description EXTRAM bit Cleared to access internal XRAM using movx @ Ri/ @ DPTR. EXTRAM Set to access external memory. Programmed by hardware after Power-up ...

  • Page 26

    Reset 10.1 Introduction The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 10-1. Reset schematic 10.2 Reset Input The Reset input can be used to force a reset pulse longer than the internal reset ...

  • Page 27

    Figure 10-3. Recommended Reset Output Schematic 4235K–8051–05/08 VDD + RST VDD 1K RST VSS AT89C51RD2/ED2 AT89C51XD2 To other on-board circuitry 27 ...

  • Page 28

    Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an ...

  • Page 29

    Figure 11-2. Power Fail Detect Vcc VPFDP VPFDM Reset Vcc When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at ...

  • Page 30

    ... Auto-reload Mode The auto-reload mode configures Timer 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel C51 Microcontroller Hardware Manual). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter as shown in Figure 12-1. In this mode the T2EX pin controls the direction of count. ...

  • Page 31

    Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1) 12.2 Programmable Clock-output In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock generator (See Figure 12-2). The input clock increments TL2 at frequency F edly counts to ...

  • Page 32

    It is possible to use Timer baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the RCAP2H and ...

  • Page 33

    Bit Number Reset Value = 0000 0000b Bit addressable 4235K–8051–05/08 Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK ...

  • Page 34

    Table 12-2. T2MOD - Timer 2 Mode Control Register (C9h Bit Number Reset Value = XXXX XX00b Not bit addressable AT89C51RD2/ED2 34 T2MOD Register ...

  • Page 35

    Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time ...

  • Page 36

    The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR set when the PCA timer overflows. Figure 13-1. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH ...

  • Page 37

    Table 13-1. CMOD - PCA Counter Mode Register (D9h) 7 CIDL Bit Number Reset Value = 00XX X000b Not bit addressable The CCON register contains the run control bit for the PCA ...

  • Page 38

    Table 13-2. CCON - PCA Counter Control Register (D8h Bit Number Reset Value = 00X0 0000b Bit addressable The watchdog timer function is implemented in Module 4 (See Figure 13-4). ...

  • Page 39

    Figure 13-2. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered • ...

  • Page 40

    Table 13-3 shows the CCAPMn settings for the various PCA functions. Table 13-3. CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) ...

  • Page 41

    Table 13-4. ECOMn There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a ...

  • Page 42

    Table 13-6. CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register ...

  • Page 43

    PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on ...

  • Page 44

    Figure 13-4. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match could ...

  • Page 45

    Figure 13-5. PCA High Speed Output Mode Write to Reset CCA PnL Write to CCAPnH 0 1 Enable Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other- wise an unwanted match could happen. ...

  • Page 46

    Figure 13-6. PCA PWM Mode 13.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, ...

  • Page 47

    The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also ...

  • Page 48

    Serial I/O Port The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Univer- sal Asynchronous Receiver and Transmitter (UART) ...

  • Page 49

    Figure 14-3. UART Timings in Modes 2 and 3 14.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition ...

  • Page 50

    Slave C:SADDR1111 0010b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit 1.To communicate with slave ...

  • Page 51

    Registers Table 14-1. SADEN - Slave Address Mask Register (B9h) 7 Reset Value = 0000 0000b Not bit addressable Table 14-2. SADDR - Slave Address Register (A9h) 7 Reset Value = 0000 0000b Not bit addressable 14.4 Baud Rate ...

  • Page 52

    Table 14-3. TCLK (T2CON 14.4.1 Internal Baud Rate Generator (BRG) When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL ...

  • Page 53

    Table 14-4. SCON - Serial Control Register (98h) 7 FE/SM0 Bit Number Reset Value = 0000 0000b Bit addressable 4235K–8051–05/08 SCON Register SM1 SM2 REN Bit Mnemonic Description Framing ...

  • Page 54

    Table 14-5. Baud Rates 115200 57600 38400 28800 19200 9600 4800 Table 14-6. Baud Rates 4800 2400 1200 The baud rate generator can be used for mode (refer to Figure 14-4.), but also for mode 0 for ...

  • Page 55

    Table 14-9. SBUF - Serial Buffer Register for UART (99h) 7 Reset Value = XXXX XXXXb Table 14-10. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) 7 Reset Value = 0000 0000b ...

  • Page 56

    Table 14-11. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT89C51RD2/ED2 EXF2 RCLK TCLK Bit Mnemonic ...

  • Page 57

    Table 14-12. PCON Register PCON - Power Control Register (87h) 7 SMOD1 Bit Number Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a ...

  • Page 58

    Table 14-13. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Number Reset Value = XXX0 0000b Not bit addressable AT89C51RD2/ED2 BRR Bit ...

  • Page 59

    Keyboard Interface The AT89C51RD2/ED2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as ...

  • Page 60

    Registers Table 15-1. KBF-Keyboard Flag Register (9Eh) 7 KBF7 Bit Number Reset Value = 0000 0000b This register is read only access, all flags are automatically cleared by reading the register. ...

  • Page 61

    Table 15-2. KBE-Keyboard Input Enable Register (9Dh) 7 KBE7 Bit Number Reset Value = 0000 0000b 4235K–8051–05/08 KBE Register KBE6 KBE5 KBE4 Bit Mnemonic Description Keyboard line 7 Enable ...

  • Page 62

    Table 15-3. KBLS-Keyboard Level Selector Register (9Ch) 7 KBLS7 Bit Number Reset Value = 0000 0000b AT89C51RD2/ED2 62 KBLS Register KBLS6 KBLS5 KBLS4 Bit Mnemonic Description Keyboard line 7 ...

  • Page 63

    Serial Port Interface (SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communica- tion between the MCU and peripheral devices, including other MCUs. 16.1 Features Features of the SPI Module include the following: • Full-duplex, three-wire synchronous ...

  • Page 64

    SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out of the devices through their MOSI and MISO lines driven by the Master for eight clock cycles which allows to ...

  • Page 65

    Functional Description Figure 16-2 Figure 16-2. SPI Module Block Diagram 16.3.1 Operating Modes The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI Module ...

  • Page 66

    Figure 16-3. Full-Duplex Master-Slave Interconnection 16.3.1.1 Master Mode The SPI operates in Master mode when the Master bit, MSTR Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the ...

  • Page 67

    Figure 16-4. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 16-5. Data Transmission Format (CPHA = 1) ...

  • Page 68

    Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a ...

  • Page 69

    Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. Mode Fault flag, MODF: This bit becomes set to indicate that the level on the ...

  • Page 70

    Bit Number Reset Value = 0001 0100b Not bit addressable 16.3.5.2 Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • ...

  • Page 71

    Bit Number Reset Value = 00X0 XXXXb Not Bit addressable 16.3.5.3 Serial Peripheral DATa Register (SPDAT) The Serial Peripheral Data Register ter. A write to SPDAT places data directly into the shift register. No ...

  • Page 72

    Interrupt System The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These ...

  • Page 73

    Registers The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors addresses are the same as standard C52 devices. ...

  • Page 74

    Table 17-3. IEN0 - Interrupt Enable Register (A8h Bit Number Reset Value = 0000 0000b Bit addressable AT89C51RD2/ED2 74 IENO Register ET2 ES Bit Mnemonic Description ...

  • Page 75

    Table 17-4. IPL0 - Interrupt Priority Register (B8h Bit Number Reset Value = X000 0000b Bit addressable 4235K–8051–05/08 IPL0 Register PPCL PT2L PSL Bit Mnemonic Description Reserved ...

  • Page 76

    Table 17-5. IPH0 - Interrupt Priority High Register (B7h Bit Number Reset Value = X000 0000b Not bit addressable AT89C51RD2/ED2 76 IPH0 Register PPCH PT2H PSH Bit ...

  • Page 77

    Table 17-6. IEN1 - Interrupt Enable Register (B1h Bit Number Reset Value = XXXX X000b Bit addressable 4235K–8051–05/08 IEN1 Register Bit Mnemonic Description - ...

  • Page 78

    Table 17-7. IPL1 - Interrupt Priority Register (B2h Bit Number Reset Value = XXXX X000b Bit addressable AT89C51RD2/ED2 78 IPL1 Register Bit Mnemonic Description ...

  • Page 79

    Table 17-8. IPH1 - Interrupt Priority High Register (B3h Bit Number Reset Value = XXXX X000b Not bit addressable 4235K–8051–05/08 IPH1 Register Bit Mnemonic ...

  • Page 80

    Power Management 18.1 Introduction Two power reduction modes are implemented in the AT89C51RD2/ED2. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the ...

  • Page 81

    Power-Down Mode The Power-Down mode places the AT89C51RD2/ED2 in a very low power state. Power-Down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-Down mode is preserved, i.e., the program counter, ...

  • Page 82

    Reset initializes the AT89C51RD2/ED2 and vectors the CPU to address 0000h. 3. Generate an enabled external Keyboard interrupt (same behavior as external interrupt). Note: Note: Table ...

  • Page 83

    Registers Table 18- Bit Number 7 Reset Value= XXXX 0000b 4235K–8051–05/08 PCON Register PCON (S87:h) Power configuration Register Bit Mnemonic Description Reserved - The value read from ...

  • Page 84

    Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT (WDTRST) SFR. The WDT is ...

  • Page 85

    Table 19-2. WDTPRG - Watchdog Timer Out Register (0A7h Bit Number Reset Value = XXXX X000 19.2 WDT during Power-down and Idle In Power-down mode the oscillator stops, which means ...

  • Page 86

    ONCE Mode (ON- Chip Emulation) The ONCE mode facilitates testing and debugging of systems using AT89C51RD2/ED2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C51RD2/ED2; the following sequence ...

  • Page 87

    Power-off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by V applied to the device and could be generated for ...

  • Page 88

    Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with exter- nal program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...

  • Page 89

    ... EEPROM Data Memory This feature is available only for the AT89C51ED2 device. The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read or write access to the EEPROM memory is done with a MOVX instruction. ...

  • Page 90

    Figure 23-1. Recommended EEPROM Data Write Sequence 23.2 Read Data The following procedure is used to read the data stored in the EEPROM memory: • Check EEBUSY flag • If the user application interrupts routines use XRAM memory space: Save ...

  • Page 91

    Figure 23-2. Recommended EEPROM Data Read Sequence 23.3 Registers Table 23-1. EECON (0D2h) EEPROM Control Register 7 - Bit Number 4235K–8051–05/08 EEPROM Data Read Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON ...

  • Page 92

    Bit Number 1 0 Reset Value = XXXX XX00b Not bit addressable AT89C51RD2/ED2 92 Bit Mnemonic Description Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write or Read to the EEE EEPROM. Clear to map ...

  • Page 93

    Flash/EEPROM Memory The Flash memory increases EEPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 64K bytes of program memory organized respectively in 512 pages of 128 bytes. This memory is both parallel and serial In-System ...

  • Page 94

    Flash Registers and Memory Map The AT89C51RD2/ED2 Flash memory uses several registers for its management: • Hardware register can only be accessed through the parallel programming modes which are handled by the parallel programmer. • Software registers are in ...

  • Page 95

    ... Software Registers Several registers are used in factory and by parallel programmers. These values are used by Atmel ISP. These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: • ...

  • Page 96

    ... Do not clear this bit. Reserved - Do not clear this bit. Reserved - Do not clear this bit. User Memory Lock Bits LB1-0 See Table 24-5 Default value Description 0FFh FFh 58h Atmel D7h C51 X2, Electrically Erasable ECh AT89C51RD2/ED2 64KB AT89C51RD2/ED2 64KB, EFh Revision LB1 4235K–8051–05/08 ...

  • Page 97

    Table 24-5. Program Lock Bits Security Level Note: 24.4 Flash Memory Status AT89C51RD2/ED2 parts are delivered in standard with the ISP ROM bootloader. After ISP or parallel programming, the possible contents of the Flash memory are summarized ...

  • Page 98

    Figure 24-2. Diagram Context Description Access Via Specific Protocol Access From User Application 24.6.2 Acronyms ISP: In-System Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Byte HW: Hardware Byte AT89C51RD2/ED2 98 Bootloader Flash Memory 4235K–8051–05/08 ...

  • Page 99

    Functional Description Figure 24-3. Bootloader Functional Description External Host with Specific Protocol Communication On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol ...

  • Page 100

    Bootloader Functionality The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions ( PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application ...

  • Page 101

    ... User Application 4235K–8051–05/08 RESET If BLJB = 0 then ENBOOT Bit (AUXR1) is Set else ENBOOT Bit (AUXR1) is Cleared Yes (PSEN = and ALE =1 or Not Connected) Hardware Condition? BLJB BLJB = 0 ENBOOT = 1 BSB = 00h ? SBV = FCh ? USER BOOT LOADER PC= [SBV]00h AT89C51RD2/ED2 Atmel BOOT LOADER 101 ...

  • Page 102

    ISP Protocol Description 24.7.1 Physical Layer The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 2 bits • Flow control: none • Baudrate: autobaud is performed by the bootloader ...

  • Page 103

    Functional Description 24.8.1 Software Security Bits (SSB) The SSB protects any Flash access from ISP command. The command "Program Software Security Bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY ...

  • Page 104

    ... An initialization step must be performed after each Reset. After microcontroller reset, the boot- loader waits for an autobaud sequence (see section ‘Autobaud Performances’). When the communication is initialized, the protocol depends on the record type requested by the host. FLIP, a software utility to implement ISP programming with a PC, is available from the Atmel web site. 24.9.2 Communication Initialization The host initializes the communication by sending a ’ ...

  • Page 105

    Table 24-8. Frequency (MHz) Baudrate (kHz) 4800 9600 19200 38400 57600 115200 Frequency (MHz) Baudrate (kHz) 2400 4800 9600 19200 38400 57600 115200 24.9.4 Command Data Stream Protocol All commands are sent using the same flow. Each frame sent by ...

  • Page 106

    ... Write/Program Commands Description This flow is common to the following frames: • Flash/EEPROM Programming Data Frame • EOF or Atmel Frame (only Programming Atmel Frame) • Config Byte Programming Data Frame • Baud Rate Frame Figure 24-9. Write/Program Flow Host Send Write Command ...

  • Page 107

    ... Example Programming Data (write 55h at address 0010h in the Flash) HOST BOOTLOADER Programming Atmel function (write SSB to level 2) HOST BOOTLOADER Writing Frame (write BSB to 55h) HOST BOOTLOADER 24.9.6 Blank Check Command Description Figure 24-10. Blank Check Flow Host Send Blank Check Command ...

  • Page 108

    Example Blank Check ok HOST BOOTLOADER Blank Check ok at address xxxx HOST BOOTLOADER Blank Check with checksum error HOST BOOTLOADER AT89C51RD2/ED2 108 : 05 0000 04 0000 7FFF 0000 04 0000 7FFF 01 78 ...

  • Page 109

    Display Data Description Figure 24-11. Display Flow Host Send Display Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Display Data All Data Read COMMAND FINISHED 24.9.7.1 Example Display data from address 0000h to ...

  • Page 110

    ... Reading Frame • EOF Frame/ Atmel Frame (only reading Atmel Frame) Figure 24-12. Read Flow Host Send Read Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Value of Data COMMAND FINISHED 24.9.8.1 Example 24.9.9 ISP Commands Summary Table 24-9 ...

  • Page 111

    Table 24-9. ISP Commands Summary (Continued) Command Command Name 03h Write Function 04h Display Function 05h Read Function 07h Program EEPROM data 4235K–8051–05/08 Data[0] Data[1] 00h 20h 01h 40h 80h C0h 03h 00h 04h 00h 00h 05h 01h 00h 06h ...

  • Page 112

    ... IAP. These API are executed by the bootloader. To call the corresponding API, the user must use a set of Flash_api routines which can be linked with the application. Example of Flash_api routines are available on the Atmel web site on the software application note: C Flash Drivers for the AT89C51RD2/ED2 The API calls description and arguments are shown in 24 ...

  • Page 113

    Table 24-10. API Call Summary (Continued) Command R1 A PROGRAM SSB 05h XXh New BSB PROGRAM BSB 06h value New SBV PROGRAM SBV 06h value READ SSB 07h XXh READ BSB 07h XXh READ SBV 07h XXh Number of PROGRAM ...

  • Page 114

    Characteristics E 25.1 Absolute Maximum Ratings I = industrial ........................................................-40 ° ° C Storage Temperature .................................... -65 ° 150 ° C Voltage ......................................-0. 6. ...

  • Page 115

    T = -40°C to +85° 0V =2.7V to 5.5V and MHz (both internal and external code execution =4.5V to 5.5V and MHz (internal ...

  • Page 116

    Port Ports 1, 2 and Maximum total I for all output pins exceeds the test condition than the listed test conditions. 7. The maximum dV/dt value specifies ...

  • Page 117

    Figure 25-4. Clock Signal Waveform for I 25.3 AC Parameters 25.3.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand ...

  • Page 118

    External Program Memory Characteristics Table 25-1. Table 25-2. AT89C51RD2/ED2 118 Symbol Description Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid ...

  • Page 119

    Table 25-3. 25.3.3 External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 25.3.4 External Data Memory Characteristics 4235K–8051–05/08 AC Parameters for a Variable Clock Symbol Type Standard Clock T Min ...

  • Page 120

    Table 25-4. Table 25-5. AT89C51RD2/ED2 120 Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ T ...

  • Page 121

    Table 25-6. 25.3.5 External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 4235K–8051–05/08 AC Parameters for a Variable Clock Standard Symbol Type Clock T Min RLRH T Min 6 T ...

  • Page 122

    External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 25.3.7 Serial Port Timing - Shift Register Mode Table 25-7. Table 25-8. AT89C51RD2/ED2 122 T LLDV T LLWL T AVDV T LLAX A0-A7 T ...

  • Page 123

    Table 25-9. 25.3.8 Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 25.3.9 External Clock Drive Waveforms 25.3.10 AC Testing Input/Output Waveforms INPUT/OUTPUT AC inputs during testing are driven at ...

  • Page 124

    Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ± 20 mA. 25.3.12 ...

  • Page 125

    Figure 25-5. Internal Clock Signals STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST ...

  • Page 126

    ... Possible Order Entries Part Number Data EEPROM AT89C51RD2-SLSUM AT89C51RD2-RLTUM No (1) AT89C51RD2-RDTUM (1) AT89C51RD2-SMSUM AT89C51ED2-SLSUM AT89C51ED2-RLTUM Yes AT89C51ED2- SMSUM AT89C51ED2-RDTUM Note: 1. For PLCC68 and VQFP64 packages, please contact Atmel sales office for availability. AT89C51RD2/ED2 126 Temperature Supply Voltage Range Industrial & 2.7V - 5.5V Green Package ...

  • Page 127

    Packaging Information 27.1 PLCC44 4235K–8051–05/08 AT89C51RD2/ED2 127 ...

  • Page 128

    STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm ...

  • Page 129

    VQFP44 4235K–8051–05/08 AT89C51RD2/ED2 129 ...

  • Page 130

    STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT ...

  • Page 131

    PLCC68 4235K–8051–05/08 AT89C51RD2/ED2 131 ...

  • Page 132

    VQFP64 AT89C51RD2/ED2 132 4235K–8051–05/08 ...

  • Page 133

    ... Changes from 4235B -06/03 to 4235C - 08/03 1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode for Vcc = 4.5V to 5.5V and internal code execution. 2. Added PDIL40 Packaging for AT89C51ED2. 28.3 Changes from 4235C - 08/03 to 4235D - 12/03 1. Improved explanations throughout the document. ...

  • Page 134

    Features .................................................................................................... 1 1 Description ............................................................................................... 2 2 Block Diagram .......................................................................................... 3 3 SFR Mapping ............................................................................................ 4 4 Pin Configurations ................................................................................... 9 5 Port Types .............................................................................................. 14 6 Oscillator ................................................................................................ 15 7 Enhanced Features ................................................................................ 17 8 Dual Data Pointer ...

  • Page 135

    Serial I/O Port ......................................................................................... 48 15 Keyboard Interface ................................................................................ 59 16 Serial Port Interface (SPI) ...................................................................... 63 17 Interrupt System .................................................................................... 72 18 Power Management ............................................................................... 80 19 Hardware Watchdog Timer ................................................................... 84 20 ONCE 21 Power-off Flag ........................................................................................ ...

  • Page 136

    Electrical Characteristics .................................................................... 114 26 Ordering Information ........................................................................... 126 27 Packaging Information ........................................................................ 127 28 Document Revision History ................................................................ 133 4235K–8051–05/08 24.3 Flash Registers and Memory Map ...................................................................94 24.4 Flash Memory Status....................................................................................... 97 24.5 Memory Organization ......................................................................................97 24.6 Bootloader ...

  • Page 137

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...