AT89C51RD2-SLSIM Atmel, AT89C51RD2-SLSIM Datasheet - Page 85

• Manufacturer Part Number: AT89C51RD2-SLSIM
• Description: IC 8051 MCU FLASH 64K 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RD2-SLSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

19.2
4235K–8051–05/08
WDT during Power-down and Idle
Table 19-2.
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode the user does not need to service the WDT. There are 2 methods of exiting Power-
down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power-down mode. When Power-down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the AT89C51RD2/ED2 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service
routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is bet-
ter to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51RD2/ED2 while in Idle mode, the user should always set up a timer that will periodically
exit Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic
WDTPRG Register
Bit
S2
S1
S0
6
-
-
-
-
-
-
Description
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2 S1 S0Selected Time-out
0
0
0
0
1
1
1
1
00
01
10 (2
11
00
01 (2
10
11
5
-
16
19
(2
(2
- 1) machine cycles, 65. 5 ms @ F
(2
(2
- 1) machine cycles, 542 ms @ F
(2
(2
14
15
17
18
20
21
- 1) machine cycles, 16. 3 ms @ F
- 1) machine cycles, 32.7 ms @ F
- 1) machine cycles, 131 ms @ F
- 1) machine cycles, 262 ms @ F
- 1) machine cycles, 1.05 ms @ F
- 1) machine cycles, 2.09 ms @ F
4
-
3
-
OSCA
AT89C51RD2/ED2
OSCA
OSCA
OSCA
=12 MHz
S2
OSCA
OSCA
OSCA
2
OSCA
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
S1
1
S0
0
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