ATMEGA162V-8AJ Atmel, ATMEGA162V-8AJ Datasheet

IC MCU AVR 16K 5V 8MHZ 44-TQFP

ATMEGA162V-8AJ

Manufacturer Part Number
ATMEGA162V-8AJ
Description
IC MCU AVR 16K 5V 8MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA162V-8AJ

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA162V-8AJ
Manufacturer:
Atmel
Quantity:
10 000
Features
High-performance, Low-power AVR
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 16K Bytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1K Bytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
– 35 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF
– 1.8 - 5.5V for ATmega162V
– 2.7 - 5.5V for ATmega162
– 0 - 8 MHz for ATmega162V (see
– 0 - 16 MHz for ATmega162 (see
Capture Modes
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
®
Figure 114 on page
Figure 113 on page
8-bit Microcontroller
(1)
266)
266)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega162
ATmega162V
Summary
2513KS–AVR–07/09

Related parts for ATMEGA162V-8AJ

ATMEGA162V-8AJ Summary of contents

Page 1

... PDIP, 44-lead TQFP, and 44-pad MLF • Operating Voltages – 1.8 - 5.5V for ATmega162V – 2.7 - 5.5V for ATmega162 • Speed Grades – MHz for ATmega162V (see – MHz for ATmega162 (see ® 8-bit Microcontroller (1) Figure 113 on page 266) ...

Page 2

Pin Figure 1. Pinout ATmega162 Configurations Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is ...

Page 3

Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize ...

Page 4

... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is a powerful microcontroller that provides a highly flexi- ble and cost effective solution to many embedded control applications. ...

Page 5

The timed sequence for changing the Watchdog Time-out period is disabled. See Sequences for Changing the Configuration of the Watchdog Timer” on page 56 • The double buffering of the USART Receive Registers is disabled. See AVR UART – ...

Page 6

Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins ...

Page 7

... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ...

Page 8

Register Summary Address Name Bit 7 (0xFF) Reserved – .. Reserved – (0x9E) Reserved – (0x9D) Reserved – (0x9C) Reserved – (0x9B) Reserved – (0x9A) Reserved – (0x99) Reserved – (0x98) Reserved – (0x97) Reserved – (0x96) Reserved – (0x95) ...

Page 9

Address Name Bit 7 (0x60) Reserved – 0x3F (0x5F) SREG I 0x3E (0x5E) SPH SP15 0x3D (0x5D) SPL SP7 UBRR1H URSEL1 (2) (2) 0x3C (0x5C) UCSR1C URSEL1 0x3B (0x5B) GICR INT1 0x3A (0x5A) GIFR INTF1 0x39 (0x59) TIMSK TOIE1 0x38 ...

Page 10

Address Name Bit 7 0x01 (0x21) UCSR1B RXCIE1 0x00 (0x20) UBRR1L Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debug- ger specific documentation for details on how to ...

Page 11

Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 12

Mnemonics Operands Description BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate LD Rd, X Load Indirect ...

Page 13

Mnemonics Operands Description Clear Half Carry Flag in SREG CLH MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 2513KS–AVR–07/09 ATmega162/V Operation H ← None (see specific descr. for Sleep function) None (see specific ...

Page 14

... Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (QFN/MLF) ATmega162/V 14 Ordering Code Package ATmega162V-8AI 44A ATmega162V-8PI 40P6 ATmega162V-8MI 44M1 (2) ATmega162V-8AU 44A (2) ATmega162V-8PU 40P6 (2) ATmega162V-8MU 44M1 ATmega162-16AI 44A ATmega162-16PI 40P6 ATmega162-16MI 44M1 (2) ATmega162-16AU 44A (2) ATmega162-16PU 40P6 ...

Page 15

Packaging Information 44A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...

Page 16

A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). ...

Page 17

... Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 2513KS–AVR–07/ Pin #1 Corner D2 Pin #1 Option A 1 Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad 1.0 mm Body, Lead Pitch 0 ...

Page 18

Errata The revision letter in this section refers to the revision of the ATmega162 device. ATmega162, all There are no errata for this revision of ATmega162. However, a proposal for solving problems regarding the JTAG instruction IDCODE is presented below. ...

Page 19

... Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Revision History Changes from Rev. 1. Updated 2513J-08/ Updated the last page with Atmel’s new adresses. Rev. 2513K-07/09 Changes from Rev. 1. Updated 2513I-04/07 to Rev. 2. Added 2513J-08/07 3 ...

Page 20

Renamed and updated “On-chip Debug System” to Debug System” on page 4. Updated 5. Updated 6. Updated description for the JTD bit on 7. Added note on JTAGEN in 8. Updated Absolute Maximum Ratings* and DC Characteristics in istics” ...

Page 21

Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02 Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02 2513KS–AVR–07/09 15. Updated Figure 29 on page 210. 16. Removed Table 114, “External RC Oscillator, Typical Frequencies page 265. 17. Updated “Electrical Characteristics” on page 1. ...

Page 22

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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