ATMEGA48V-10AI Atmel, ATMEGA48V-10AI Datasheet - Page 13

IC AVR MCU 4K 5V 10MHZ 32-TQFP

ATMEGA48V-10AI

Manufacturer Part Number
ATMEGA48V-10AI
Description
IC AVR MCU 4K 5V 10MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48V-10AI

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA48V-12AI
ATMEGA48V-12AI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48V-10AI
Manufacturer:
Atmel
Quantity:
10 000
6.6.1
6.7
2545S–AVR–07/10
Instruction Execution Timing
SPH and SPL – Stack Pointer High and Stack Pointer Low Register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 6-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
Figure 6-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6-5.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
Result Write Back
RAMEND
RAMEND
SP15
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
SP7
R/W
R/W
15
7
clk
clk
CPU
RAMEND
RAMEND
CPU
SP14
SP6
R/W
R/W
14
6
RAMEND
RAMEND
SP13
R/W
R/W
SP5
13
5
CPU
T1
T1
, directly generated from the selected clock source for the
RAMEND
RAMEND
SP12
R/W
R/W
SP4
12
4
RAMEND
RAMEND
SP11
R/W
R/W
SP3
T2
11
T2
3
RAMEND
RAMEND
SP10
ATmega48/88/168
SP2
R/W
R/W
10
2
T3
T3
RAMEND
RAMEND
SP9
SP1
R/W
R/W
9
1
RAMEND
RAMEND
SP8
SP0
R/W
R/W
8
0
T4
T4
SPH
SPL
13

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