ATMEGA48V-10AI Atmel, ATMEGA48V-10AI Datasheet - Page 215

IC AVR MCU 4K 5V 10MHZ 32-TQFP

ATMEGA48V-10AI

Manufacturer Part Number
ATMEGA48V-10AI
Description
IC AVR MCU 4K 5V 10MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48V-10AI

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA48V-12AI
ATMEGA48V-12AI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48V-10AI
Manufacturer:
Atmel
Quantity:
10 000
21.5
21.5.1
21.5.2
2545S–AVR–07/10
Overview of the TWI Module
SCL and SDA Pins
Bit Rate Generator Unit
The TWI module is comprised of several submodules, as shown in
drawn in a thick line are accessible through the AVR data bus.
Figure 21-9. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note
Slew-rate
Address Match Unit
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Spike
Filter
Bus Interface Unit
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(TWSR)
State Machine and
Control Unit
Status control
ATmega48/88/168
Bit Rate Generator
Control Register
Bit Rate Register
Figure
Prescaler
(TWCR)
(TWBR)
21-9. All registers
215

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