ATMEGA88-20AJ Atmel, ATMEGA88-20AJ Datasheet - Page 208

IC MCU AVR 8K 5V 20MHZ 32-TQFP

ATMEGA88-20AJ

Manufacturer Part Number
ATMEGA88-20AJ
Description
IC MCU AVR 8K 5V 20MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88-20AJ

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA88-24AJ
ATMEGA88-24AJ

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA88-20AJ
Manufacturer:
Atmel
Quantity:
10 000
21. 2-wire Serial Interface
21.1
21.2
21.2.1
208
Features
2-wire Serial Interface Bus Definition
ATmega48/88/168
TWI Terminology
The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 21-1. TWI Bus Interconnection
The following definitions are frequently encountered in this section.
Table 21-1.
Term
Master
Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400 kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up When AVR is in Sleep Mode
Compatible with Philips I
SDA
SCL
TWI Terminology
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
Device 1
2
C protocol
Device 2
Device 3
........
Device n
V
CC
R1
R2
2545S–AVR–07/10

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