ATMEGA88-20MJ Atmel, ATMEGA88-20MJ Datasheet - Page 137

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ATMEGA88-20MJ

Manufacturer Part Number
ATMEGA88-20MJ
Description
IC MCU AVR 8K 5V 20MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88-20MJ

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA88-24MJ
ATMEGA88-24MJ
ATmega48/88/168
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
< f
/2) given a 50/50% duty cycle. Since the edge detector uses
ExtClk
clk_I/O
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
/2.5.
clk_I/O
An external clock source can not be prescaled.
(1)
Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1
clk
I/O
Clear
PSRSYNC
T0
Synchronization
T1
Synchronization
clk
clk
T1
T0
T1/T0)
Note:
1. The synchronization logic on the input pins (
is shown in
Figure
16-1.
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2545S–AVR–07/10

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