DSPIC30F4013T-20I/PT Microchip Technology, DSPIC30F4013T-20I/PT Datasheet
DSPIC30F4013T-20I/PT
Specifications of DSPIC30F4013T-20I/PT
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DSPIC30F4013T-20I/PT Summary of contents
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... The conditions leading to a Stack Error Trap have been clarified. 3. Restrictions on the instructions that can be used at or near the end loop have been clarified. 2004 Microchip Technology Inc. dsPIC30F FAMILY REFERENCE MANUAL 4. The timing for Program Space Visibility (PSV) operations has been clarified and the effect of instruction stalls on PSV has been corrected ...
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... If the restrictions above are not followed, the DO loop may execute incorrectly. 4. Page 2-34, Section 2.9.2.5.1 Last Instruction Restrictions On page 2-34, Section 2.9.2.5.1 Last Instruction Restrictions, the following bullet should be added to the end of the bulleted list: 6. DISI instruction DS80169E-page 2 2004 Microchip Technology Inc. ...
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... Map (Continued), in the first row of the table, correct bits names for bit 8 through bit 12 in the CORCON register as follows: TABLE 1: CORCON BIT NAMES Bit Location Bit Name in CORCON (Incorrect) (Please read as EDT 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual Bit Name US EDT DL2 DS80169E-page 3 ...
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... Value at POR DS80169E-page 4 U-0 R/W-0 R/W-0 — BWM<3:0> R/W-0 R/W-0 R/W-0 YWM<3:0> Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 XWM<3:0> bit Bit is unknown 2004 Microchip Technology Inc. ...
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... NVMCON Register Values for RTSP Program and Erase Operations Memory Type Flash PM Data EEPROM Configuration Register Note: The device configuration registers may be written to a new value without performing an erase cycle. 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual . NVMCON Register Values Operation Erase 1 row (32 instr. words) Program 1 row (32 instr ...
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... PM address W Register EA TBLPAG Reg NVMADR Register NVMADRU Register 8 bits 16 bits NVMADR register loaded with contents of W register EA used during last table-write instruction. NVMADRU register loaded with contents of TBLPAG register during last table-write instruction EA<0> is Byte Select 2004 Microchip Technology Inc. ...
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... Program 1 data word into data EEPROM 0x05 = Program 1 row (16 data words) into data EEPROM 0x08 = Program 1 data word into device configuration register Legend Readable bit S = Settable bit ‘0’ = Bit is cleared 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual U-0 U-0 U-0 — — ...
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... R = Readable bit -n = Value at POR DS80169E-page 8 R/W-x R/W-x R/W-x R/W-x NVMADR<15:8> R/W-x R/W-x R/W-x NVMADR<7:0> Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-x bit 8 R/W-x R/W-x R/W-x bit Bit is unknown 2004 Microchip Technology Inc. ...
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... RTSP is 32 instruction word locations. Therefore important that an image of these locations be stored in general purpose RAM before an erase cycle is initiated. An erase cycle must be performed on any previously written locations before any programming is done. 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual DS80169E-page 9 ...
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... NVMADRU and NVMADR registers. The above code example could be modified to perform a ‘dummy’ table write operation to capture the program memory erase address. DS80169E-page 10 NVMCON , NVMADRU , #0x55,W0 NVMKEY NVMKEY 2004 Microchip Technology Inc. ...
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... TBLWTH W3,[W0++] MOV #LOW_WORD_2,W2 MOV #HIGH_BYTE_2,W3 TBLWTL W2 [W0] , TBLWTH W3 [W0++] , MOV #LOW_WORD_3,W2 MOV #HIGH_BYTE_3,W3 TBLWTL W2 [W0] , TBLWTH W3,[W0++] ........ ........ MOV #LOW_WORD_31,W2 MOV #HIGH_BYTE_31,W3 TBLWTL W2 [W0] , TBLWTH W3,[W0++] 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual ; 1st_program_word ; 2nd_program_word ; 3rd_program_word ; 4th_program_word ; 32nd_program_word DS80169E-page 11 ...
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... Registers Associated with Interrupt Controller On page 6-43, Table 6-3: Special Function Registers Associated with Interrupt Controller, row 3, Bit 0, SFR Name: IFS0, should be replaced with the following: INT0IF DS80169E-page 12 #literal” instruction or a “GOTO #literal” instruction, where 2004 Microchip Technology Inc. ...
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... Note: The OSCCON register description and functionality may vary depending on the clock sources available on the selected device. Please refer to the specific device data sheet for additional details on this register.. 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual R-y U-0 U-0 ...
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... To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater. DS80169E-page 14 ; pointer to OSCCON ; first unlock code ; second unlock code ; write first unlock code ; write second unlock code ; ABORT the switch 2004 Microchip Technology Inc. ...
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... When not used with the PWM module, these pins may be used as general purpose I/O or another multiplexed function. Each fault pin has its own interrupt vector, interrupt flag bit, interrupt enable bit, and interrupt priority bits associated with it. 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual R/W-0 R/W-0 R/W-0 PTMR < ...
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... On page 17-37, Table 17-5 Converting Three Inputs, Four Times and Four Inputs, One Timer Per Interrupt, the initialization of the SMPI <3:0> (ADCON2<5:2>) bits should be modified as follows: SMPI<3:0> = 0011 DS80169E-page 16 = 5V). DD vs. Device AD ) must be selected to ensure a AD 2004 Microchip Technology Inc. ...
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... For correct A/D conversions, the A/D conversion clock (T minimum T time of 667 nsec (for V AD Also remove Table 18-1: Typical T Operating Frequencies. 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual ), and the internal sampling switch (R IC 10-bit A/D Converter Analog Input Model V ...
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... T = leakage current at the pin due to various junctions = interconnect resistance IC = sampling switch resistance SS = sample/hold capacitance (from DAC) HOLD ) must HOLD ) impedance SS . The combined imped- HOLD , is 2 After the Sampling Switch HOLD = DAC capacitance = negligible PIN 2004 Microchip Technology Inc. ...
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... U1STA MOV #0x8800,W0 MOV W0,U1MODE BSET U1STA,#UTXEN BSET IEC0,#U1TXIE BSET IEC0,#U1RXIE 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual ; Set Baudrate ; Set UART TX interrupt priority ; ; ; Set UART RX interrupt priority ; ; ; Enable UART for 8-bit data parity, 1 STOP bit, ...
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... Transmit/Receive (UART1), Address Detect Enabled ; Set Baudrate ; Set UART TX interrupt priority ; ; ; Set UART RX interrupt priority ; ; ; Enable address detect ; UART1 enabled for 9-bit data parity, 1 STOP bit, ; wakeup enabled ; Enable transmit ; Enable transmit interrupts ; Enable receive interrupts 2004 Microchip Technology Inc. ...
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... Bit Location Bit Name in SFR (Incorrect) (Please read as) IFS0<14> BCLIF IFS0<13> I2CIF IEC0<14> BCLIE IEC0<13> I2CIE IPC3<10:8> BCLIP<2:0> IPC3<6:4> I2CIP<2:0> 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 2 C Control R/W-1 R/W-0 R/W-0 HC SCLREL IPMIEN A10M R/W-0 R/W-0 R/W ACKDT ...
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... CAN2 module registers should be changed/corrected as follows: DS80169E-page 22 f BCG<11:0> CSCK 2 S Data 2 S Data 2 S data transfers will be MSb left justified. The MSb of the data word will be CY – 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F Family Reference Manual DS80169E-page 23 ...
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... Family Reference Manual DS80169E-page 24 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F Family Reference Manual DS80169E-page 25 ...
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... Family Reference Manual DS80169E-page 26 2004 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F Family Reference Manual DS80169E-page 27 ...
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... Family Reference Manual DS80169E-page 28 2004 Microchip Technology Inc. ...
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... Segment Configuration Bit Group, add the following note to the end. Note: If the code protection configuration fuse group (FGS<GCP:GWRP>) bits have been programmed, an erase of the entire code-protected device is only possible at voltages, V 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual >= 4.5 volts. DD DS80169E-page 29 ...
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... IMV<1:0> R/W-0 U-0 QECK<2:0> — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared document correctly depicts the R/W-0 CEID bit 8 U-0 U-0 U-0 — — — bit Bit is unknown 2004 Microchip Technology Inc. ...
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... Erratas #19, #24 and #25. New Errata #32 – updated document and Figure 17-21. Added new Figure 17-21a 65/2004) Revision E (06/2004) Additions made to Errata #30, Errata #32 and Errata #34. Errata #44 was updated. Added new Errata #33 and Errata #35. 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual DS80169E-page 31 ...
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... Family Reference Manual NOTES: DS80169E-page 32 2004 Microchip Technology Inc. ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Waegenburghtplein 4 NL-5152 JR, Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 05/28/04 2004 Microchip Technology Inc. ...