DSPIC30F4013T-20I/PT Microchip Technology, DSPIC30F4013T-20I/PT Datasheet - Page 6

• Manufacturer Part Number: DSPIC30F4013T-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IP

5.2
The Enhanced ICSP mode is entered by holding PGC
and PGD high, and then raising MCLR/V
(high voltage), as illustrated in
the code memory, data EEPROM and Configuration
bits can be efficiently programmed using the program-
ming executive commands that are serially transferred
using PGC and PGD.
FIGURE 5-2:
DS70102K-page 6
Note 1: The sequence that places the device into
MCLR/V
V
PGD
PGC
DD
2: Before entering Enhanced ICSP mode,
3: When in Enhanced ICSP mode, the SPI
Entering Enhanced ICSP Mode
V
IHH
PP
Enhanced ICSP mode places all unused
I/Os in the high-impedance state.
clock switching must be disabled using
ICSP, by programming the FCKSM<1:0>
bits in the FOSC Configuration register to
‘11’ or ‘10’.
output pin (SDO1) will toggle while the
device is being programmed.
P6
ENTERING ENHANCED
ICSP™ MODE
PGD = Input
P7
Figure
5-2. In this mode,
PP
to V
IHH
5.3
Before a chip can be programmed, it must be erased.
The Bulk Erase command (ERASEB) is used to perform
this task. Executing this command with the MS
command field set to 0x3 erases all code memory, data
EEPROM and code-protect Configuration bits. The
Chip Erase process sets all bits in these three memory
regions to ‘1’.
Since non-code-protect Configuration bits cannot be
erased, they must be manually set to ‘1’ using multiple
PROGC commands. One PROGC command must be
sent for each Configuration register (see
“Configuration Bits
If Advanced Security features are enabled, then indi-
vidual Segment Erase operations would need to be
performed, depending on which segment needs to be
programmed at a given stage of system programming.
The user should have the flexibility to select specific
segments for programming.
5.4
The term “Blank Check” means to verify that the device
has been successfully erased and has no programmed
memory cells. A blank or erased memory cell reads as
‘1’. The following memories must be blank checked:
• All implemented code memory
• All implemented data EEPROM
• All Configuration bits (for their default value)
The Device ID registers (0xFF0000:0xFF0002) can be
ignored by the Blank Check since this region stores
device information that cannot be erased. Additionally,
all unimplemented memory space should be ignored
from the Blank Check.
The QBLANK command is used for the Blank Check. It
determines if the code memory and data EEPROM are
erased by testing these memory regions. A ‘BLANK’ or
‘NOT BLANK’ response is returned. The READD
command is used to read the Configuration registers. If
it is determined that the device is not blank, it must be
erased (see
attempting to program the chip.
Note:
Chip Erase
Blank Check
The Device ID registers cannot be erased.
These registers remain intact after a Chip
Erase is performed.
Section 5.3 “Chip
Programming”).
© 2010 Microchip Technology Inc.
Erase”) before
Section 5.7