DSPIC30F4013T-20I/PT Microchip Technology, DSPIC30F4013T-20I/PT Datasheet - Page 9

• Manufacturer Part Number: DSPIC30F4013T-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IP

5.6.3
Once the data EEPROM is programmed, the contents
of memory can be verified to ensure that the
programming was successful. Verification requires the
data EEPROM to be read back and compared against
the copy held in the programmer’s buffer. The READD
command reads back the programmed data EEPROM.
Alternatively, the programmer can perform the
verification once the entire device is programmed using
a checksum computation, as described in
“Checksum
5.7
5.7.1
The dsPIC30F has Configuration bits stored in seven
16-bit registers. These bits can be set or cleared to
select various device configurations. There are two
types of Configuration bits: system-operation bits and
code-protect bits. The system-operation bits determine
the power-on settings for system-level components
such as the oscillator and Watchdog Timer. The code-
protect bits prevent program memory from being read
and written.
TABLE 5-4:
© 2010 Microchip Technology Inc.
FCKSM<1:0>
FOS<1:0>
FPR<3:0>
Note:
Bit Field
Configuration Bits Programming
PROGRAMMING VERIFICATION
TBLRDL instructions executed within a
REPEAT loop must not be used to read
from Data EEPROM. Instead, it is
recommended to use PSV access.
OVERVIEW
Computation”.
FOSC
FOSC
FOSC
FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2010 AND
dsPIC30F6010/6011/6012/6013/6014
Register
Clock Switching Mode
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Oscillator Source Selection on POR
11 = Primary Oscillator
10 = Internal Low-Power RC Oscillator
01 = Internal Fast RC Oscillator
00 = Low-Power 32 kHz Oscillator (Timer1 Oscillator)
Primary Oscillator Mode
1111 = ECIO w/PLL 16X – External Clock mode with 16X PLL. OSC2 pin is I/O
1110 = ECIO w/PLL 8X – External Clock mode with 8X PLL. OSC2 pin is I/O
1101 = ECIO w/PLL 4X – External Clock mode with 4X PLL. OSC2 pin is I/O
1100 = ECIO – External Clock mode. OSC2 pin is I/O
1011 = EC – External Clock mode. OSC2 pin is system clock output (F
1010 = Reserved (do not use)
1001 = ERC – External RC Oscillator mode. OSC2 pin is system clock output
1000 = ERCIO – External RC Oscillator mode. OSC2 pin is I/O
0111 = XT w/PLL 16X – XT Crystal Oscillator mode with 16X PLL
0110 = XT w/PLL 8X – XT Crystal Oscillator mode with 8X PLL
0101 = XT w/PLL 4X – XT Crystal Oscillator mode with 4X PLL
0100 = XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal)
001x = HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal)
000x = XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal)
(F
Section 6.8
OSC
/4)
The FOSC Configuration register has three different
register descriptions, based on the device. The FOSC
Configuration
dsPIC30F2010 and dsPIC30F6010/6011/6012/6013/
6014 devices are shown in
The FOSC Configuration register description for the
dsPIC30F4011/4012 and dsPIC30F5011/5013 devices
is shown in
The FOSC Configuration register description for
all remaining
dsPIC30F3010/3011/3012/3013,
4013, dsPIC30F5015 and dsPIC30F6011A/6012A/
6013A/ 6014A) is shown in
correct register descriptions for your target processor.
The FWDT, FBORPOR, FBS, FSS, FGS and FICD
Configuration registers are not device-dependent. The
register descriptions for these Configuration registers
are shown in
The Device Configuration register maps are shown in
Table 5-8
Note:
Description
through
If user software performs an erase opera-
tion on the configuration fuse, it must be
followed by a write operation to this fuse
with the desired value, even if the desired
value is the same as the state of the
erased fuse.
Table
Table
register
5-5.
Table
devices
5-7.
5-11.
Table
Table
description
(dsPIC30F2011/2012,
5-4.
5-6. Always use the
DS70102K-page 9
dsPIC30F3014/
OSC
for
/4)
the