ATMEGA88V-10AU Atmel, ATMEGA88V-10AU Datasheet - Page 226

• Manufacturer Part Number: ATMEGA88V-10AU
• Description: IC AVR MCU 8K 10MHZ 1.8V 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88V-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: 2-Wire, SPI, USART, Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3 bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 32TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 21-3.
226
Status Code
(TWSR)
Prescaler Bits
are 0
0x08
0x10
0x38
0x40
0x48
0x50
0x58
ATmega48/88/168
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
A START condition has been
transmitted
A repeated START condition
has been transmitted
Arbitration lost in SLA+R or
NOT ACK bit
SLA+R has been transmitted;
ACK has been received
SLA+R has been transmitted;
NOT ACK has been received
Data byte has been received;
ACK has been returned
Data byte has been received;
NOT ACK has been returned
Status codes for Master Receiver Mode
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-
out losing control over the bus.
To/from TWDR
Load SLA+R
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
Application Software Response
STA
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
STO
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
To TWCR
TWIN
T
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWE
A
X
X
X
X
X
0
1
X
X
X
0
1
X
X
X
Next Action Taken by TWI Hardware
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
2-wire Serial Bus will be released and not addressed
Slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
2545S–AVR–07/10