ATMEGA88V-10MU Atmel, ATMEGA88V-10MU Datasheet - Page 63

• Manufacturer Part Number: ATMEGA88V-10MU
• Description: IC AVR MCU 8K 10MHZ 1.8V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: 2-Wire, SPI, USART, Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3 bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 10MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• For Use With: ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4.1
11.5
11.5.1
2545S–AVR–07/10
Register Description
Moving Interrupts Between Application and Boot Space, ATmega88 and ATmega168
MCUCR – MCU Control Register
The MCU Control Register controls the placement of the Interrupt Vector table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section
Self-Programming, ATmega88 and ATmega168” on page 268
changes of Interrupt Vector tables, a special write procedure must be followed to change the
IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
This bit is not available in ATmega48.
Bit
0x35 (0x55)
Read/Write
Initial Value
Address Labels Code
;
.org 0x1C00
0x1C00
0x1C02
0x1C04
...
0x1C32
;
0x1C33
0x1C34
0x1C35
0x1C36
0x1C37
0x1C38
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
Write Self-Programming, ATmega88 and ATmega168” on page 268
RESET: ldi
R
7
–
0
jmp
jmp
jmp
...
jmp
out
ldi
out
sei
<instr>
R
6
–
0
RESET
EXT_INT0
EXT_INT1
...
SPM_RDY
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
R
5
–
0
PUD
R/W
4
0
Comments
; Reset handler
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
“Boot Loader Support – Read-While-Write
R
3
–
0
ATmega48/88/168
for details. To avoid unintentional
“Boot Loader Support – Read-While-
R
2
–
0
for details on Boot Lock bits.
IVSEL
R/W
1
0
IVCE
R/W
0
0
MCUCR
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