TS80C32X2-VCED Atmel, TS80C32X2-VCED Datasheet

IC 8051 MCU ROMLESS 5V 44VQFP

TS80C32X2-VCED

Manufacturer Part Number
TS80C32X2-VCED
Description
IC 8051 MCU ROMLESS 5V 44VQFP
Manufacturer
Atmel
Series
80Cr
Datasheet

Specifications of TS80C32X2-VCED

Core Processor
8051
Core Size
8-Bit
Speed
60/30MHz
Connectivity
UART/USART
Peripherals
POR
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TS80C32X2-VCED
Manufacturer:
Atmel
Quantity:
10 000
Features
Description
TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions
of the 80C51 CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM
capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and an X2 speed improve-
ment mechanism.
The fully static design of the TS80C52X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C52X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
80C52 Compatible
High-speed Architecture
40 MHz at 5V, 30 MHz at 3V
X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
Dual Data Pointer
On-chip ROM/EPROM (8Kbytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Asynchronous Port Reset
Interrupt Structure with
Full Duplex Enhanced UART
Low EMI (Inhibit ALE)
Power Control Modes
Once Mode (On-chip Emulation)
Power Supply: 4.5 - 5.5V, 2.7 - 5.5V
Temperature Ranges: Commercial (0 to 70
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratchpad RAM
– 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V)
– 6 Interrupt Sources
– 4 Level Priority Interrupt System
– Framing Error Detection
– Automatic Address Recognition
– Idle Mode
– Power-down Mode
– Power-off Flag
o
C) and Industrial (-40 to 85
o
C)
8-bit
Microcontroller
8 Kbytes
ROM/OTP,
ROMless
TS80C32X2
TS87C52X2
TS80C52X2
AT80C32X2
AT80C52X2
AT87C52X2
Rev. 4184G–8051–09/06

Related parts for TS80C32X2-VCED

TS80C32X2-VCED Summary of contents

Page 1

... In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. C) and Industrial (- 8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless TS80C32X2 TS87C52X2 TS80C52X2 AT80C32X2 AT80C52X2 AT87C52X2 Rev. 4184G–8051–09/06 ...

Page 2

... Block Diagram TS8xCx2X2 2 Table 1. Memory Size ROM (bytes) TS80C32X2 0 TS80C52X2 8k TS87C52X2 0 (3) (3) XTAL1 EUART XTAL2 ALE/ PROG PSEN CPU EA/VPP (2) Timer 0 RD Timer 1 (2) WR (2) (2) Notes: 1. Alternate function of Port 1 2. Alternate function of Port 3 EPROM (bytes (1) (1) ROM RAM /EPROM Timer2 256x8 ...

Page 3

SFR Mapping 4184G–8051–09/06 The Special Function Registers (SFRs) of the TS80C52X2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, ...

Page 4

Table 2. All SFRs with their address and their reset value Bit Addressable 0/8 1/9 F8h B F0h 0000 0000 E8h ACC E0h 0000 0000 PSW h 0000 0000 C8 T2CON T2MOD h 0000 0000 XXXX XX00 ...

Page 5

Pin Configuration P1 P1.1 / T2EX 2 P1.2 3 P1.3 4 P1.4 5 P1 P1.7 RST 9 P3.0/RxD 10 PDIL/ P3.1/TxD 11 12 CDIL40 P3.2/INT0 P3.3/INT1 13 P3.4/ P3.5/T1 P3.6/WR 16 ...

Page 6

TS8xCx2X2 6 Mnemonic Pin Number Type Name and Function VQFP DIL LCC 1 Vss1 39- 43- P0.0-P0.7 37-30 I P1.0-P1.7 1-8 2-9 40-44 I/O 1-3 1 ...

Page 7

Mnemonic Pin Number Type Name and Function VQFP DIL LCC 1 Reset ALE/PROG (I) Address ...

Page 8

TS80C52X2 Enhanced Features X2 Feature Description TS8xCx2X2 8 In comparison to the original 80C52, the TS80C52X2 implements some new features, which are : • The X2 option • The Dual Data Pointer • The 4 level interrupt priority system • ...

Page 9

... X2 Clear to select 12 clock periods per machine cycle (STD mode, F Set to select 6 clock periods per machine cycle (X2 mode, F Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel.com) TS8xCx2X2 STD Mode ...

Page 10

Dual Data Pointer Register (Ddptr) Figure 3. Use of Dual Pointer 7 0 DPS AUXR1(A2H) TS8xCx2X2 10 The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual ...

Page 11

Application 4184G–8051–09/06 Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and ...

Page 12

... The Auto-reload mode configures timer 16-bit timer or event counter with auto- matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin controls the direction of count ...

Page 13

Figure 4. Auto-reload Mode Up/Down Counter (DCEN = 1) XTAL1 F XTAL Programmable Clock-output 4184G–8051–09/06 (: mode) :12 F OSC T2 C/T2 T2CONreg (DOWN COUNTING RELOAD FFh (8-bit) TL2 (8-bit) RCAP2L RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) In ...

Page 14

Figure 5. Clock-Out Mode C/ XTAL1 T2 T2EX TS8xCx2X2 mode) TR2 T2CON reg TL2 (8-bit) RCAP2L (8-bit) Toggle Q D T2MOD reg EXF2 T2CON reg EXEN2 T2CON reg TH2 (8-bit) OVERFLOW RCAP2H (8-bit) ...

Page 15

Table 5. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 ...

Page 16

TS8xCx2X2 16 Table 6. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...

Page 17

TS80C52X2 Serial I/O Port Framing Error Detection Figure 6. Framing Error Block Diagram SM0/FE SMOD1 Figure 7. UART Timings in Mode 1 RXD RI SMOD0=X FE SMOD0=1 4184G–8051–09/06 The serial I/O port in the TS80C52X2 is compatible with the serial ...

Page 18

Figure 8. UART Timings in Modes 2 and 3 RXD RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition Given Address TS8xCx2X2 Start Data byte bit The automatic address recognition feature is enabled when ...

Page 19

Broadcast Address Reset Addresses 4184G–8051–09/06 1111 0000b). For slave A, bit for slaves B and C, bit don’t care bit. To communicate with slaves B and C, but not slave A, the master ...

Page 20

TS8xCx2X2 20 Table 9. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. ...

Page 21

Table 10. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...

Page 22

Interrupt System Figure 9. Interrupt Control System INT0 TF0 INT1 TF1 RI TI TF2 EXF2 Individual Enable TS8xCx2X2 22 The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 ...

Page 23

Thus within each priority level there is a second priority structure determined by the polling sequence. Table 12. IE Register IE - Interrupt Enable Register (A8h) 7 ...

Page 24

TS8xCx2X2 24 Table 13. IP Register IP - Interrupt Priority Register (B8h PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 25

Table 14. IPH Register IPH - Interrupt Priority High Register (B7h PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 26

Idle mode Power-down Mode Figure 10. Power-down Exit Waveform INT0 INT1 XTAL1 Active phase TS8xCx2X2 26 An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the ...

Page 27

Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. Note: If idle ...

Page 28

TM ONCE Mode (ON Chip Emulation) TS8xCx2X2 28 The ONCE mode facilitates testing and debugging of systems using TS80C52X2 with- out removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C52X2; the ...

Page 29

Power-off Flag 4184G–8051–09/06 The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and could ...

Page 30

Reduced EMI Mode TS8xCx2X2 30 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...

Page 31

TS80C52X2 ROM Structure ROM Lock System Encryption Array Program Lock Bits Signature bytes Verify Algorithm 4184G–8051–09/06 The TS80C52X2 ROM memory is divided in three different arrays: • the code array:8 Kbytes. • the encryption array:64 bytes. • the signature array:4 ...

Page 32

EPROM Structure EPROM Lock System Encryption Array Program Lock Bits Signature Bytes EPROM Programming Set-up modes TS8xCx2X2 32 The TS87C52X2 is divided in two different arrays: • the code array: 8 Kbytes • the encryption array: 64 bytes In addition ...

Page 33

Definition of terms Figure 11. Set-Up Modes Configuration ...

Page 34

Programming Algorithm Verify Algorithm Figure 12. Programming and Verification Signal’s Waveform ...

Page 35

... TS80/87C52X2. Table 21. Signature Bytes Content Location Contents 30h 31h 60h 60h 60h 61h TS8xCx2X2 Comment 58h Manufacturer Code: Atmel 57h Family Code: C51 X2 2Dh Product name: TS80C52X2 ADh Product name:TS87C52X2 20h Product name: TS80C32X2 FFh Product revision number 35 ...

Page 36

... Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was run- ning under reset. In Atmel new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’ ...

Page 37

Table 22. DC Parameters in Standard Voltage (Continued) Symbol Parameter V Output High Voltage, ports Output High Voltage, port 0 OH1 V Output High Voltage,ALE, PSEN OH2 R RST Pulldown Resistor RST I Logical 0 ...

Page 38

DC Parameters for Low Voltage Table 23. DC Parameters for Low Voltage Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, RST IH V Input High Voltage, XTAL1, RST IH1 V Output Low Voltage, ports 1, ...

Page 39

Port Ports 1, 2 and Maximum total I for all output pins exceeds the test condition than the listed test conditions. 7. For other values, please contact ...

Page 40

Figure 16. I Test Condition, Power-down Mode CC Reset = Vss after a high pulse during at least 24 clock cycles Figure 17. Clock Signal Waveform for I AC Parameters Explanation of the AC Symbols TS8xCx2X2 ...

Page 41

External Program Memory Characteristics 4184G–8051–09/06 Table 28., Table 31. and Table 34. give the frequency derating formula of the AC param- eter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V ...

Page 42

TS8xCx2X2 42 Table 27. AC Parameters for Fix Clock -V X2 mode 30 MHz -M 60 MHz Speed 40 MHz equiv. Symbol Min Max Min LHLL AVLL LLAX ...

Page 43

External Program Memory Read Cycle Figure 18. External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics 4184G–8051–09/ CLCL T T LHLL LLIV T LLPL T PLPH T ...

Page 44

TS8xCx2X2 44 Table 30. AC Parameters for a Fix Clock -V X2 mode 30 MHz Speed -M 60 MHz 40 MHz equiv. Symbol Min Max Min T 130 85 RLRH T 130 85 WLWH T 100 RLDV ...

Page 45

External Data Memory Write Cycle Figure 19. External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 4184G–8051–09/06 Table 31. AC Parameters for a Variable Clock: Derating Formula Standard Symbol Type Clock T Min 6 ...

Page 46

External Data Memory Read Cycle Figure 20. External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode TS8xCx2X2 46 T LLDV T LLWL ...

Page 47

Shift Register Timing Waveforms Figure 21. Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 4184G–8051–09/06 Table 34. AC Parameters for a Variable Clock: Derating Formula Standard Symbol Type Clock ...

Page 48

EPROM Programming and Verification Characteristics EPROM Programming and Verification Waveforms Figure 22. EPROM Programming and Verification Waveforms P1.0-P1.7 P2.0-P2.5 P3.4-P3. ALE/PROG EA CONTROL SIGNALS (ENABLE) * 8KB P2.4, 16KB P2.5, 32KB: ...

Page 49

External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms Figure 23. External Clock Drive Waveforms VCC-0.5V 0.45V AC Testing Input/Output Waveforms Figure 24. AC Testing Input/Output Waveforms INPUT/OUTPUT Float Waveforms Figure 25. Float Waveforms 4184G–8051–09/06 Table 36. AC Parameters Symbol ...

Page 50

Clock Waveforms Figure 26. Clock Waveforms STATE4 CLOCK P1P2 XTAL2 ALE ...

Page 51

... TS80C32X2-LCC ROMLess TS80C32X2-LCE ROMLess TS80C32X2-VCA ROMLess TS80C32X2-VCB ROMLess TS80C32X2-VCC ROMLess TS80C32X2-VCE ROMLess TS80C32X2-MIA ROMLess TS80C32X2-MIB ROMLess TS80C32X2-MIC ROMLess TS80C32X2-MIE ROMLess TS80C32X2-LIA ROMLess TS80C32X2-LIB ROMLess TS80C32X2-LIC ROMLess TS80C32X2-LIE ROMLess TS80C32X2-VIA ROMLess TS80C32X2-VIB ROMLess TS80C32X2-VIC ROMLess TS80C32X2-VIE ROMLess AT80C32X2-3CSUM ROMLess AT80C32X2-SLSUM ROMLess AT80C32X2-RLTUM ...

Page 52

Table 37. Possible Ordering Entries (Continued) (3) Part Number Memory Size AT80C32X2-RLTUL ROMLess AT80C32X2-3CSUV ROMLess AT80C32X2-SLSUV ROMLess AT80C32X2-RLTUV ROMLess TS80C52X2zzz-MCA 8K ROM TS80C52X2zzz-MCB 8K ROM TS80C52X2zzz-MCC 8K ROM TS80C52X2zzz-MCE 8K ROM TS80C52X2zzz-LCA 8K ROM TS80C52X2zzz-LCB 8K ROM TS80C52X2zzz-LCC 8K ROM ...

Page 53

Table 37. Possible Ordering Entries (Continued) (3) Part Number Memory Size AT80C52X2zzz-3CSUL 8K ROM AT80C52X2zzz-SLSUL 8K ROM AT80C52X2zzz-RLTUL 8K ROM AT80C52X2zzz-3CSUV 8K ROM AT80C52X2zzz-SLSUV 8K ROM AT80C52X2zzz-RLTUV 8K ROM TS87C52X2-MCA 8K OTP TS87C52X2-MCB 8K OTP TS87C52X2-MCC 8K OTP TS87C52X2-MCE 8K ...

Page 54

Table 37. Possible Ordering Entries (Continued) (3) Part Number Memory Size AT87C52X2-3CSUM 8K OTP AT87C52X2-SLSUM 8K OTP AT87C52X2-RLTUM 8K OTP AT87C52X2-3CSUL 8K OTP AT87C52X2-SLSUL 8K OTP AT87C52X2-RLTUL 8K OTP AT87C52X2-3CSUV 8K OTP AT87C52X2-SLSUV 8K OTP AT87C52X2-RLTUV 8K OTP Notes: 1. ...

Page 55

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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