AT91SAM7X256-CU Atmel, AT91SAM7X256-CU Datasheet
AT91SAM7X256-CU
Specifications of AT91SAM7X256-CU
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AT91SAM7X256-CU Summary of contents
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... Kbytes (AT91SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) • Single Cycle Access MHz in Worst Case Conditions • ...
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... Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit Power Width Modulation Controller (PWMC) • One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs and I • One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ® • ...
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... Ethernet, CAN wired and Zigbee networks. 1.1 Configuration Summary of the AT91SAM7X512/256/128 The AT91SAM7X512, AT91SAM7X256 and AT91SAM7X128 differ only in memory sizes. 1-1 summarizes the configurations of the three devices. Table 1-1. Device ...
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AT91SAM7X512/256/128 Block Diagram Figure 2-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADVREF AT91SAM7X512/256/128 Preliminary 4 AT91SAM7X512/256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK ...
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Signal Description Table 3-1. Signal Description List Signal Name Function Voltage Regulator and ADC Power VDDIN Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash and USB Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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Table 3-1. Signal Description List (Continued) Signal Name Function AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN1 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK ...
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Package The AT91SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS- compliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 tion is given in the Mechanical Characteristics section. Figure 4-1. AT91SAM7X512/256/128 Preliminary 8 shows the orientation of ...
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LQFP Pinout Table 4-1. Pinout in 100-lead LQFP Package 1 ADVREF 26 2 GND 27 3 AD4 28 4 AD5 29 5 AD6 30 6 AD7 31 7 VDDOUT 32 8 VDDIN 33 9 PB27/AD0 34 10 PB28/AD1 ...
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TFBGA Package Outline Figure 4-2 description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-2. 4.4 100-ball TFBGA Pinout Pinout in 100-ball TFBGA Package Pin Signal Name Pin A1 PA22/PGMD10 C6 A2 PA21/PGMD9 C7 ...
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Power Considerations 5.1 Power Supplies The AT91SAM7X512/256/128 has six types of power supply pins and integrates a voltage regu- lator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...
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Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...
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I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven VDDIO, ...
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PIO Controller Lines All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programma- ble pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM high-performance 32-bit instruction set – Thumb high code ...
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Embedded Flash Controller – Embedded Flash interface three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and ...
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... Protection Mode to secure contents of the Flash • 128 Kbytes of Fast SRAM – Single-cycle access at full speed 8.2 AT91SAM7X256 • 256 Kbytes of Flash Memory – 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – ...
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Figure 8-1. AT91SAM7X512/256/128 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF AT91SAM7X512/256/128 Preliminary 18 Internal ...
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... Internal Flash • The AT91SAM7X512 features two banks (dual plane) of 256 Kbytes of Flash. • The AT91SAM7X256 features one bank (single plane) of 256 Kbytes of Flash. • The AT91SAM7X128 features one bank (single plane) of 128 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000 also accessible at address 0x0 after the reset, if GPNVM bit 2 is set and before the Remap Command ...
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... The Flash of the AT91SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the AT91SAM7X256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words. • The Flash of the AT91SAM7X128 is organized in 512 pages of 256 bytes (single plane). It reads as 32,768 32-bit words ...
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... One EFC is embedded in the AT91SAM7X256/128 to control the single plane of 256/128 KBytes. 8.5.3 Lock Regions 8.5.3.1 AT91SAM7X512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands ...
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Flash Programming Interface, is forbidden. This ensures the confidentiality of the code pro- grammed in the Flash. This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can ...
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Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped at address 0x0 when the ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and ...
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Figure 9-1. NRST XOUT PLLRC PA0-PA30 PB0-PB30 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset Timer ...
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Reset Controller • Based on one power-on reset cell and one brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST pin ...
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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 ...
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Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • four programmable ...
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... Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x275C 0A40 (VERSION 0) for AT91SAM7X512 – Chip ID is 0x275B 0940 (VERSION 0) for AT91SAM7X256 – Chip ID is 0x275A 0740 (VERSION 0) for AT91SAM7X128 9.6 Periodic Interval Timer • ...
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Real-time Timer • 32-bit free-running counter with alarm running on prescaled SLCK • Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controllers • Two PIO Controllers, each controlling 31 I/O lines • Fully programmable through set/clear registers • ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 Mbytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 ...
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Peripheral Multiplexing on PIO Lines The AT91SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 RXD0 PA1 TXD0 PA2 SCK0 PA3 RTS0 PA4 CTS0 PA5 RXD1 PA6 TXD1 PA7 SCK1 PA8 RTS1 PA9 CTS1 PA10 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 ETXCK/EREFCK PB1 ETXEN PB2 ETX0 PB3 ETX1 PB4 ECRS PB5 ERX0 PB6 ERX1 PB7 ERXER PB8 EMDC PB9 EMDIO PB10 ...
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Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.3 • 10 and 100 Mbit/s operation • Full- and half-duplex operation • Statistics Counter Registers • MII/RMII interface to the physical layer • ...
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One, two or three bytes internal address registers for easy Serial Memory access • 7-bit or 10-bit slave addressing • Sequential read/write operations 10.9 USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial ...
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Pulse generation – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs • Five internal clock inputs, as defined in Table 10-4. TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 ...
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Suspend/resume logic 10.14 CAN Controller • Fully compliant with CAN 2.0A and 2.0B • Bit rates up to 1Mbit/s • Eight object oriented mailboxes each with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B ...
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ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM ing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, ...
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ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state ...
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Table 11-1. User and System Mode R10 R11 R12 R13 R14 PC CPSR Registers are unbanked registers. This means that each of them refers to the same ...
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A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 11.2.4.2 Status Registers ...
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Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC 11.2.6 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded ...
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Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 11-3 Table 11-3. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH ...
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Debug and Test Features 12.1 Description The AT91SAM7X Series features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The ...
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Application Examples 12.3.1 Debug Environment Figure 12-2 standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example AT91SAM7X512/256/128 Preliminary 46 shows a complete debug environment example. The ICE/JTAG interface is used ...
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Test Environment Figure 12-3 ter. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example 12.4 Debug ...
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... The AT91SAM7X512 Debug Unit Chip ID value is 0x275C 0A40 on 32-bit width. The AT91SAM7X256 Debug Unit Chip ID value is 0x275B 0940 on 32-bit width. The AT91SAM7X128 Debug Unit Chip ID value is 0x275A 0740 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. ...
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ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant not possible to switch directly between JTAG and ICE operations. A chip reset must be per- formed after JTAGSEL ...
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Table 12-2. Number AT91SAM7X512/256/128 Preliminary 50 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 163 162 PA7/SCK1/SPI0_NPCS1 161 160 ERASE 159 158 PB27/TIOA2/PWM0/AD0 157 156 155 PB28/TIOB2/PWM1/AD1 154 153 152 PB29/PCK1/PWM2/AD2 151 150 149 PB30/PCK2/PWM3/AD3 148 147 146 PA8/RTS1/SPI0_NPCS2 ...
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Table 12-2. Number 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 129 128 PA14/SPI0_NPCS2/IRQ1 127 126 125 PA15/SPI0_NPCS3/TCLK2 124 123 122 PA16/SPI0_MISO 121 120 119 PA17/SPI0_MOSI 118 117 116 PA18/SPI0_SPCK 115 114 113 PB9/EMDIO 112 111 ...
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Table 12-2. Number AT91SAM7X512/256/128 Preliminary 52 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 96 95 PB15/ERXDV/ECRSDV PB17/ERXCK/SPI0_NPCS3 PB7/ERXER PB12/ETXER/TCLK0 PB0/ETXCK/EREFCK/PCK0 PB1/ETXEN 79 78 ...
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Table 12-2. Number 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 63 62 PA20/CANTX PA21/TF/SPI1_NPCS0 PA22/TK/SPI1_SPCK PB16/ECOL/SPI1_NPCS3 PB4/ECRS PA23/TD/SPI1_MOSI 46 45 ...
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Table 12-2. Number AT91SAM7X512/256/128 Preliminary 54 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 30 29 PB20/PWM1/PCK0 PB21/PWM2/PCK2 PB22/PWM3/PCK2 PB23/TIOA0/DCD1 PB24/TIOB0/DSR1 PB25/TIOA1/DTR1 13 12 ...
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... PART NUMBER[27:12]: Product Part Number AT91SAM7X512: 0x5B18 AT91SAM7X256: 0x5B17 AT91SAM7X128: 0x5B16 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. AT91SAM7X512: JTAG ID Code value is 05B1_803F AT91SAM7X256: JTAG ID Code value is 05B1_703F AT91SAM7X128: JTAG ID Code value is 05B1_303F 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary ...
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AT91SAM7X512/256/128 Preliminary 56 6120H–ATARM–17-Feb-09 ...
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Reset Controller (RSTC) The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the ...
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Functional Description 13.2.1 Reset Controller Overview The Reset Controller is made NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • ...
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NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in ...
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Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed ...
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User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR The NRST input signal is resynchronized with SLCK to insure proper behav- ior ...
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Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock ...
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Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the ...
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Figure 13-7. Software Reset AT91SAM7X512/256/128 Preliminary 64 SLCK Any MCK Freq. Write RSTC_CR Resynch. 1 cycle proc_nreset if PROCRST=1 RSTTYP Any periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 SRCMP in RSTC_SR Processor Startup = 3 cycles XXX 0x3 = Software ...
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Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is ...
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Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Power-up Reset • Brownout Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed ...
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Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a ...
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Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register AT91SAM7X512/256/128 Preliminary 68 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset - 0x0000_0000 0x0000_0000 6120H–ATARM–17-Feb-09 ...
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Reset Controller Control Register Register Name: RSTC_CR Access Type: Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets ...
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Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened ...
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Reset Controller Mode Register Register Name: RSTC_MR Access Type: Read-write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the ...
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AT91SAM7X512/256/128 Preliminary 72 6120H–ATARM–17-Feb-09 ...
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Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt or/and triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1. ...
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock advis- able to read this register twice at the ...
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Real-time Timer (RTT) User Interface Table 14-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Name RTT_MR RTT_AR RTT_VR RTT_SR Access Reset Value Read-write 0x0000_8000 Read-write 0xFFFF_FFFF Read-only ...
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Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read-write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time ...
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Real-time Timer Alarm Register Register Name: RTT_AR Access Type: Read-write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.4.3 Real-time Timer Value Register Register Name: ...
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Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred ...
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Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1. ...
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Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...
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Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 0 ...
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Periodic Interval Timer (PIT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM7X512/256/128 Preliminary 82 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only ...
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Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: Read-write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the ...
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Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the ...
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Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
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Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
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Figure 16-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN ...
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Watchdog Timer (WDT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register 16.4.1 Watchdog Timer Control Register Register Name: WDT_CR Access Type: Write-only – – ...
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Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read-write Once 31 30 – – WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. ...
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Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read ...
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Voltage Regulator Mode Controller (VREG) 17.1 Overview The Voltage Regulator Mode Controller contains one Read-write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. ...
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Voltage Regulator Power Controller (VREG) User Interface Table 17-1. Register Mapping Offset Register 0x60 Voltage Regulator Mode Register 17.2.1 Voltage Regulator Mode Register Register Name: VREG_MR Access Type: Read-write 31 30 – – – – ...
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Memory Controller (MC) 18.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a bus arbiter, an address decoder, an abort ...
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Functional Description The Memory Controller handles the internal ASB bus and arbitrates the accesses three masters made up of: • A bus arbiter • An address decoder • An abort status • A misalignment ...
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Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte ...
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Abort Status There are two reasons for an abort to occur: • access to an undefined address • an access to a misaligned address. When an abort occurs, a signal is sent back to all the masters, regardless of ...
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The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particularly difficult to detect in the debug phase. As the requested address is saved in the Abort Status Register and the address of the ...
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Memory Controller (MC) User Interface Base Address: 0xFFFFFF00 Table 18-1. Register Mapping Offset Register 0x00 MC Remap Control Register 0x04 MC Abort Status Register 0x08 MC Abort Address Status Register 0x10-0x5C Reserved 0x60 EFC0 Configuration Registers (1) 0x70 EFC1 ...
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MC Remap Control Register Register Name: MC_RCR Access Type: Write-only Offset: 0x0 31 30 – – – – – – – – • RCB: Remap Command Bit 0: No effect. 1: This Command ...
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MC Abort Status Register Register Name: MC_ASR Access Type: Read-only Reset Value: 0x0 Offset: 0x04 31 30 – – – – – – – – • UNDADD: Undefined Address Abort Status 0: The ...
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MST_PDC: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. • MST_ARM: ARM Abort Source 0: The last aborted access was not due to ...
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MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Offset: 0x08 • ABTADD: Abort Address This field contains the address of the last aborted access. AT91SAM7X512/256/128 ...
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... The Embedded Flash size, the page size and the lock region organization are described in the product definition section. Table 19-1. AT91SAM7X512 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Product Specific Lock and General-purpose NVM Bits AT91SAM7X256 AT91SAM7X128 Denomination “Read Operations” on page “Write Operations” on page ...
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Figure 19-1. Embedded Flash Memory Mapping 19.2.2 Read Operations An optimized controller manages embedded Flash reads. A system 32-bit buffers is added in order to start access at following address during the second read, thus increasing perfor- ...
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Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0 Master Clock ARM Request (16-bit) Code Fetch @Byte 0 @Byte 2 Flash Access Bytes 0-3 Buffer (32 bits) Data To ARM Bytes 0-1 Note: When FWS is equal ...
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Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3 3 Wait State Cycles Master Clock ARM Request (16-bit) Code Fetch @Byte 0 Flash Access Bytes 0-3 Buffer (32 bits) Data To ARM Note: When FWS is equal ...
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To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command number. As soon as the MC_FCR register is written, the FRDY flag is automati- cally cleared. Once the current command ...
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Figure 19-5. Command State Chart In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle Number (FMCN) in the Flash Mode Register MC_FMR must be correctly programmed (see Flash Mode Register” on page 19.2.4.1 Flash ...
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Figure 19-6. Example of Partial Page Programming: 32 bits wide ... 16 words ... 16 words ...
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Erase All operation is allowed only if there are no lock bits set. Thus least one lock region is locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written ...
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General-purpose NVM Bits General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not apply to EFC1 on the AT91SAM7X512.) These general-purpose bits are dedicated to protect other parts of the product. They can be set ...
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When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the ...
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Embedded Flash Controller (EFC ) User Interface The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register ...
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MC Flash Mode Register Register Name: MC_FMR Access Type: Read-write Offset: (EFC0) 0x60 Offset: (EFC1) 0x70 31 30 – – – – NEBP – • FRDY: Flash Ready Interrupt Enable 0: Flash Ready ...
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FMCN: Flash Microsecond Cycle Number Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond. When writing the rest ...
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MC Flash Command Register Register Name: MC_FCR Access Type: Write-only Offset: (EFC0) 0x64 Offset: (EFC1) 0x74 – – – – • FCMD: Flash Command This field defines the Flash commands: FCMD ...
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PAGEN: Page Number Command Write Page Command Write Page and Lock Command Erase All Command Set/Clear Lock Bit Command Set/Clear General Purpose NVM Bit Command Set Security Bit Command Note: Depending on the command, all the possible unused bits ...
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MC Flash Status Register Register Name: MC_FSR Access Type: Read-only Offset: (EFC0) 0x68 Offset: (EFC1) 0x78 31 30 LOCKS15 LOCKS14 LOCKS13 23 22 LOCKS7 LOCKS6 15 14 – – – – • FRDY: Flash Ready Status 0: ...
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Fast Flash Programming Interface (FFPI) 20.1 Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is ...
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Table 20-1. Signal Description List Signal Name Function VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL Power Supply GND Ground Main Clock Input. This input can be tied to GND. In this XIN ...
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Table 20-3. DATA[15:0] 0x0011 0x0012 0x0022 0x0032 0x0042 0x0013 0x0014 0x0024 0x0015 0x0034 0x0044 0x0025 0x0054 0x0035 0x001F 0x0016 0x001E Note: 20.2.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: • Apply GND, VDDIO, VDDCORE, ...
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Figure 20-2. Parallel Programming Timing, Write Sequence Table 20-4. Write Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Releases MODE and DATA signals 5 Sets NCMD signal 6 ...
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Table 20-5. Read Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Sets DATA signal in tristate 5 Clears NOE signal 6 Waits for NVALID low 7 8 Reads ...
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Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The ...
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Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is pro- ...
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Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the ...
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Table 20-16. Write Command (Continued) Step ... n n+1 n+2 n+3 ... 20.2.5.9 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-17. Get Version Command Step 1 2 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Handshake ...
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Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a ...
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Table 20-18. Signal Description List (Continued) Signal Name Function TST Test Mode Select PGMEN0 Test Mode Select PGMEN1 Test Mode Select TCK JTAG TCK TDI JTAG Test Data In TDO JTAG Test Data Out TMS JTAG Test Mode Select 20.3.2 ...
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Debug Comms Control Register: DCCR • Debug Comms Data Register: DCDR Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address field and a read/write bit. The data to ...
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This address must be word-aligned. The address is automatically incremented. Table 20-20. Read Command Read/Write Write Write Read Read ... Read 20.3.4.2 Flash Write Command This command is used to write the Flash ...
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All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command. Table 20-22. Full Erase Command Read/Write Write 20.3.4.4 Flash Lock Commands Lock bits can be set using WPL or ...
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Flash Security Bit Command Security bits can be set using Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. Only an event on the Erase ...
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Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-30. Get Version Command Read/Write Write Read AT91SAM7X512/256/128 Preliminary 134 DR Data GVE Version 6120H–ATARM–17-Feb-09 ...
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AT91SAM Boot Program 21.1 Overview The Boot Program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BA DBGU ...
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SAM-BA Boot The SAM-BA boot principle is to: – Check if USB Device enumeration has occurred – Check if the AutoBaudrate sequence has succeeded (see Figure 21-2. AutoBaudrate Flow Diagram – Once the communication interface is identified, the application ...
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Table 21-1. Command • Write commands: Write a byte (O), a halfword ( word (W) to the target. – Address: Address in hexadecimal. – Value: Byte, halfword or ...
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... ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. ...
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... Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details. 21.4.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration send- ing requests to the device through the control endpoint ...
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... SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available size for the user code is 122880 bytes forAT91SAM7x512, 57344 bytes for AT91SAM7X256 and 24576 bytes for AT91SAM7X128. • USB requirements: – pull-up on DDP – ...
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Peripheral DMA Controller (PDC) 22.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor intervention ...
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Functional Description 22.3.1 Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset ...
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Programming the Next Counter/Pointer registers chains the buffers. The counters are decre- mented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in ...
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Peripheral DMA Controller (PDC) User Interface Table 22-1. Register Mapping Register Offset 0x100 Receive Pointer Register 0x104 Receive Counter Register 0x108 Transmit Pointer Register 0x10C Transmit Counter Register 0x110 Receive Next Pointer Register 0x114 Receive Next Counter Register 0x118 ...
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PDC Receive Pointer Register Register Name: PERIPH_RPR Access Type: Read-write • RXPTR: Receive Pointer Address Address of the next receive transfer. 22.4.2 PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: ...
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PDC Transmit Pointer Register Register Name: PERIPH_TPR Access Type: Read-write • TXPTR: Transmit Pointer Address Address of the transmit buffer. 22.4.4 PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read-write ...
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PDC Receive Next Pointer Register Register Name: PERIPH_RNPR Access Type: Read-write • RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when ...
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PDC Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: Read-write • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer ...
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PDC Transfer Control Register Register Name: PERIPH_PTCR - Access Type: Write only 31 30 – – – – – – – – • RXTEN: Receiver Transfer Enable effect ...
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PDC Transfer Status Register Register Name: PERIPH_PTSR Access Type: Read-only 31 30 – – – – – – – – • RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. ...
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Advanced Interrupt Controller (AIC) 23.1 Overview The Advanced Interrupt Controller (AIC 8-level priority, individually maskable, vectored interrupt controller, providing handling thirty-two interrupt sources designed to sub- stantially reduce the software and real-time ...
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Application Block Diagram Figure 23-2. Description of the Application Block 23.4 AIC Detailed Block Diagram Figure 23-3. AIC Detailed Block Diagram 23.5 I/O Line Description Table 23-1. I/O Line Description Pin Name FIQ IRQ0 - IRQn AT91SAM7X512/256/128 Preliminary 152 ...
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Product Dependencies 23.6.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO control- lers. Depending on the features of the PIO controller used in the product, the pins must be programmed in ...
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Functional Description 23.7.1 Interrupt Source Control 23.7.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRC- TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal ...
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Internal Interrupt Source Input Stage Figure 23-4. 23.7.1.6 External Interrupt Source Input Stage Figure 23-5. External Interrupt Source Input Stage Source i AIC_ISCR AIC_ICCR 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Source i Edge Edge ...
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Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. • Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress ...
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External Interrupt Level Sensitive Source Figure 23-7. 23.7.2.3 Internal Interrupt Edge Triggered Source Figure 23-8. 23.7.2.4 Internal Interrupt Level Sensitive Source Figure 23-9. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or ...
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Normal Interrupt 23.7.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources (except for those programmed in Fast Forcing). Each interrupt source ...
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When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating ...
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Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re- assertion of the nIRQ to be taken into account by the core. This can happen if an inter- rupt with a higher priority than ...
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Fast Interrupt 23.7.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a ...
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In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine ...
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All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus ...
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Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associ- ated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM ...
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An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) • An interrupt occurs just a few cycles ...
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Advanced Interrupt Controller (AIC) User Interface 23.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor ...
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AIC Source Mode Register Register Name: AIC_SMR0..AIC_SMR31 Access Type: Read-write Reset Value: 0x0 31 30 – – – – – – – SRCTYPE • PRIOR: Priority Level Programs the priority level for all ...
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AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Read-write Reset Value: 0x0 • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for ...
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AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read-only Reset Value • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the ...
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AIC Interrupt Pending Register Register Name: AIC_IPR Access Type: Read-only Reset Value PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt ...
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AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read-only Reset Value – – – – – – – – • NFIQ: NFIQ Status 0 = nFIQ line is ...
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AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Disable effect ...
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AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Set effect ...
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AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type: Read-write Reset Value • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler ...
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AIC Fast Forcing Enable Register Register Name: AIC_FFER Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Enable effect ...
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AIC Fast Forcing Status Register Register Name: AIC_FFSR Access Type: Read-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature ...
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Clock Generator 24.1 Overview The Clock Generator is made PLL, a Main Oscillator, as well Oscillator . It provides the following clocks: • SLCK, the Slow Clock, which is the only permanent clock ...
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Figure 24-2. Typical Crystal Connection 24.3.2 Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the ...
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Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. 24.3.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user ...
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... The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. AT91SAM7X512/256/128 Preliminary 180 ...
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Power Management Controller (PMC) 25.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all sys- tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The ...
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Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for ...
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The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 25.6 Programmable Clock Output ...
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Setting PLL and divider: All parameters needed to configure PLL and the divider are located in the CKGR_PLLR register. The DIV field is used to control divider itself. A value between 0 and 255 can be pro- grammed. Divider ...
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If a new value for CSS field corresponds to PLL Clock, – Program the PRES field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the CSS field in ...
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PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock. Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the ...
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Clock Switching Details 25.8.1 Master Clock Switching Timings Table 25-1 selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the ...
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Figure 25-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR Figure 25-5. Change PLL Programming Write CKGR_PLLR AT91SAM7X512/256/128 Preliminary 188 Slow Clock Main Clock MCKRDY Master Clock Main Clock PLL Clock LOCK MCKRDY Master Clock Main Clock ...
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Figure 25-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PLL Clock PCKRDY PCKx Output PLL Clock is selected PCKx is enabled PCKx is disabled 189 ...
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Power Management Controller (PMC) User Interface Table 25-2. Register Mapping Offset Register 0x0000 System Clock Enable Register 0x0004 System Clock Disable Register 0x0008 System Clock Status Register 0x000C Reserved 0x0010 Peripheral Clock Enable Register 0x0014 Peripheral Clock Disable Register ...
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PMC System Clock Enable Register Register Name: PMC_SCER Access Type: Write-only 31 30 – – – – – – UDP – • UDP: USB Device Port Clock Enable effect. 1 ...
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PMC System Clock Disable Register Register Name: PMC_SCDR Access Type: Write-only 31 30 – – – – – – UDP – • PCK: Processor Clock Disable effect Disables ...
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PMC System Clock Status Register Register Name: PMC_SCSR Access Type: Read-only 31 30 – – – – – – UDP – • PCK: Processor Clock Status 0 = The Processor clock is disabled. ...
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PMC Peripheral Clock Enable Register Register Name: PMC_PCER Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Enable effect ...
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PMC Peripheral Clock Status Register Register Name: PMC_PCSR Access Type: Read-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock ...
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PMC Clock Generator Main Oscillator Register Register Name: CKGR_MOR Access Type: Read-write 31 30 – – – – – – • MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and ...
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PMC Clock Generator Main Clock Frequency Register Register Name: CKGR_MCFR Access Type: Read-only 31 30 – – – – • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 ...
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PMC Clock Generator PLL Register Register Name: CKGR_PLLR Access Type: Read-write 31 30 – – OUT 7 6 Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. • ...
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PMC Master Clock Register Register Name: PMC_MCKR Access Type: Read-write 31 30 – – – – – – – – • CSS: Master Clock Selection • PRES: Processor Clock ...
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PMC Programmable Clock Register Register Name: PMC_PCKx Access Type: Read-write 31 30 – – – – – – – – • CSS: Master Clock Selection CSS • PRES: Programmable ...