ATMEGA88PA-MU Atmel, ATMEGA88PA-MU Datasheet - Page 263

• Manufacturer Part Number: ATMEGA88PA-MU
• Description: MCU AVR 8K ISP FLASH MEM 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88PA-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.9
23.9.1
8271C–AVR–08/10
Register Description
ADMUX – ADC Multiplexer Selection Register
• Bit 7:6 – REFS[1:0]: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
Table 23-3.
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see
page
• Bit 4 – Reserved
This bit is an unused bit in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will
always read as zero.
• Bits 3:0 – MUX[3:0]: Analog Channel Selection Bits
The value of these bits selects which analog inputs are connected to the ADC. See
for details. If these bits are changed during a conversion, the change will not go in effect until this
conversion is complete (ADIF in ADCSRA is set).
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
(0x7C)
Read/Write
Initial Value
REFS1
0
0
1
1
266.
REFS0
REFS1
Voltage Reference Selections for ADC
R/W
0
1
0
1
7
0
REFS0
Voltage Reference Selection
AREF, Internal V
AV
Reserved
Internal 1.1V Voltage Reference with external capacitor at AREF pin
R/W
6
0
CC
with external capacitor at AREF pin
ADLAR
R/W
5
0
ref
turned off
R
4
–
0
MUX3
R/W
”ADCL and ADCH – The ADC Data Register” on
3
0
MUX2
R/W
2
0
MUX1
R/W
1
0
Table
MUX0
R/W
0
0
23-3. If these bits are
ADMUX
Table 23-4
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